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[Other resource] sin-genereter

Description: 首先，单片机计算出正弦波所需的ad转换数据，将此数据存入数组，然后将数据放入fifo，单片机只需读fifo，（将fifo设置成循环输出模式）就可得所需波形，另外，控制延时时间，即可控制频率。
Platform: | Size: 2133 | Author: 孙海波 | Hits:

[SCM] sin-genereter

Description: 首先，单片机计算出正弦波所需的ad转换数据，将此数据存入数组，然后将数据放入fifo，单片机只需读fifo，（将fifo设置成循环输出模式）就可得所需波形，另外，控制延时时间，即可控制频率。-First of all, single-chip microcomputer to calculate the required sine wave ad conversion data, this data into an array, and then the data Add fifo, Singlechip just read fifo, (will be set to cycle fifo output mode) can have waveform requirements, In addition, the control delay time, you can control the frequency.
Platform: | Size: 2048 | Author: 孙海波 | Hits:

[VHDL-FPGA-Verilog] THS1206

Description: FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
Platform: | Size: 1024 | Author: LX | Hits:

[VHDL-FPGA-Verilog] memtest

Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Platform: | Size: 223232 | Author: 平凡 | Hits:

[VHDL-FPGA-Verilog] fpgacis

Description: 主要是通过使用FPGA利用CIS（接触式图像传感器）进行图像采集，通过AD转换之后把数据存储到FPGA里面开辟的FIFO-Mainly through the use of FPGA utilization of CIS (non-contact image sensor) image acquisition, through the data storage after AD transform to open the FIFO FPGA inside
Platform: | Size: 1097728 | Author: 袁官福 | Hits:

[SCM] oscillograph_AVR

Description: 通过这个示波器的制作，你将会了解很多东西，比如如何运用运算放大器组合放大电路，高速AD转换器的应用、FIFO存储器的应用、AVR单片机SPI总线接口协议以及点阵液晶驱动。-Produced by the oscilloscope, you will understand many things, such as how to use the combination of amplifier op-amp, high-speed AD converter application, FIFO memory applications, AVR MCU SPI bus interface protocol and the dot matrix LCD driver.
Platform: | Size: 3500032 | Author: z1234 | Hits:

[SCM] shiboqi_51_12864

Description: 用c51单片机+12864实现示波器功能——单次触发+存储回放系统方案中信号经过直流偏置输入到模数转换芯片AD876，AD转换输出后输入到先入先出存储器。在单片机的控制下将存储在存储器中 的采样数据读取并将波形在LCD中显示，同时，可以通过两路DA输出可以在普通示波器中实时回放波形-SCM+12864 achieved using the oscilloscope function c51- Single Trigger+ storage playback system program through the DC bias signal input to analog-digital conversion chip AD876, AD converter output and input to the FIFO memory. Under the control of the microcontroller is stored in the memory of the waveform sample data read and displayed in the LCD, while the DA output by two in the ordinary oscilloscope waveform in real-time playback
Platform: | Size: 80896 | Author: minzi | Hits:

[DSP program] C6713_AD_huibian

Description: dsp c6713汇编程序。内涵：AD采样，数据处理，乘除，开放运算，fir运算，FIFO输出 对学习6713芯片汇编和了解c6713芯片有帮助-dsp c6713 assembler. Content: AD sampling, data processing, multiplication and division, open computing, fir operations, FIFO output of the learning and understanding c6713 6713 chip chip assembly help
Platform: | Size: 294912 | Author: 何鹏 | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] based-on-Xilinx-PCIe-Core-DMA

Description: 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据，DA数据。 4， DriverStudio生成的驱动代码，最大限度的提高连续传输的速率，同时降低PC的负载。 5， 用户自定义BAR2空间，可用作自定义控制。 6， 支持32位和64位操作系统。
Platform: | Size: 2329600 | Author: rosen | Hits:

[VHDL-FPGA-Verilog] fengpingPfifo

Description: 基于DE0平台实现不同时钟下采集8位AD芯片采样速率，并进行发送。采用的是FIFO模块。-8 AD chip sampling rate based on DE0 platform different clock collection and send. FIFO module.
Platform: | Size: 2219008 | Author: 吴爱东 | Hits:

[Software Engineering] ad

Description: 程序是本人亲测，可实现fpga对ads804的高速数据采集，和输出。利用了fpga的fifo和ad芯片每六个时钟数据更新一次的原理-The program I pro-test, the FPGA the ads804 high-speed data acquisition and output. The principle of use fpga fifo and ad-chip is updated once every six clock data
Platform: | Size: 2700288 | Author: 阮志强 | Hits:

[ARM-PowerPC-ColdFire-MIPS] osc-scope-use-stm32

Description: 采用stm32构成的示波器。采用STM32高性能ARM处理器作为核心控制芯片，能够满足TFT彩色波形显示，数字插值算法处理等。通过采用高速AD和FIFO器件，实现了高采样率，宽频带的技术要求。实验室测试结果表明本文的设计是正确的，各项指标均达到设计要求。-osc scope degin by stm32
Platform: | Size: 1912832 | Author: sun | Hits:

[VHDL-FPGA-Verilog] Dos_Pro---8.18

Description: 简易数字示波器，从AD接受双通道数据，存入内部fifo，并通过串口传至单片机实现波形显示-Simple digital oscilloscope, from AD to accept dual-channel data stored in the internal fifo waveform display and transmitted to the microcontroller through the serial port
Platform: | Size: 3658752 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] Quartus

Description: VERILOG AD采集程序 FIFO存储-VERILOG AD acquisition program FIFO memory
Platform: | Size: 739328 | Author: | Hits:

[VHDL-FPGA-Verilog] AD_TO_FIFO

Description: A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)
Platform: | Size: 1024 | Author: preman | Hits:

[Embeded-SCM Develop] ByteQueue

Description: 队列缓冲区设定模块，可用于串口、按键、AD等需要较大缓冲区的工程(A queue buffer setting module, which can be used for a project with a larger buffer, such as serial ports, keys, AD, etc.)
Platform: | Size: 2048 | Author: 雲山 | Hits:

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