Description: FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
- [ad_7266_32_v1_00_a] - The Verilog driver of AD7266 has been si
- [EXPT84_DAC2ADC] - FPGA+ DA conversion, ALTERA company FPGA
- [modulator] - Use FPGA to control the operation of AD9
- [TLC549] - verilog TLC549AD sampling procedures, th
- [DA] - FPGA control DAC2807 source, Verilog. A
- [da] - Serial DA FIR filter algorithm using 16
- [dac] - DA-chip SPI protocol output control does
- [Smart-AD-and-DA-Conversion] - The book named
File list (Check if you may need any files):
ad_da_ctr\adfifoda_ctr.asm.rpt
.........\adfifoda_ctr.done
.........\adfifoda_ctr.dpf
.........\adfifoda_ctr.fit.rpt
.........\adfifoda_ctr.fit.smsg
.........\adfifoda_ctr.fit.summary
.........\adfifoda_ctr.flow.rpt
.........\adfifoda_ctr.map.rpt
.........\adfifoda_ctr.map.smsg
.........\adfifoda_ctr.map.summary
.........\adfifoda_ctr.pin
.........\adfifoda_ctr.pof
.........\adfifoda_ctr.qpf
.........\adfifoda_ctr.qsf
.........\adfifoda_ctr.saf
.........\adfifoda_ctr.sim.rpt
.........\adfifoda_ctr.sof
.........\adfifoda_ctr.tan.rpt
.........\adfifoda_ctr.tan.summary
.........\adfifoda_ctr.v
.........\adfifoda_ctr.v.bak
.........\adfifoda_ctr.vwf
.........\db\add_sub_gvd.tdf
.........\..\adfifoda_ctr.asm.qmsg
.........\..\adfifoda_ctr.asm_labs.ddb
.........\..\adfifoda_ctr.cbx.xml
.........\..\adfifoda_ctr.cmp.bpm
.........\..\adfifoda_ctr.cmp.cdb
.........\..\adfifoda_ctr.cmp.ecobp
.........\..\adfifoda_ctr.cmp.hdb
.........\..\adfifoda_ctr.cmp.logdb
.........\..\adfifoda_ctr.cmp.rdb
.........\..\adfifoda_ctr.cmp.tdb
.........\..\adfifoda_ctr.cmp0.ddb
.........\..\adfifoda_ctr.cmp2.ddb
.........\..\adfifoda_ctr.cmp_bb.cdb
.........\..\adfifoda_ctr.cmp_bb.hdb
.........\..\adfifoda_ctr.cmp_bb.logdb
.........\..\adfifoda_ctr.cmp_bb.rcf
.........\..\adfifoda_ctr.dbp
.........\..\adfifoda_ctr.db_info
.........\..\adfifoda_ctr.eco.cdb
.........\..\adfifoda_ctr.eds_overflow
.........\..\adfifoda_ctr.fit.qmsg
.........\..\adfifoda_ctr.hier_info
.........\..\adfifoda_ctr.hif
.........\..\adfifoda_ctr.map.bpm
.........\..\adfifoda_ctr.map.cdb
.........\..\adfifoda_ctr.map.ecobp
.........\..\adfifoda_ctr.map.hdb
.........\..\adfifoda_ctr.map.logdb
.........\..\adfifoda_ctr.map.qmsg
.........\..\adfifoda_ctr.map_bb.cdb
.........\..\adfifoda_ctr.map_bb.hdb
.........\..\adfifoda_ctr.map_bb.logdb
.........\..\adfifoda_ctr.pre_map.cdb
.........\..\adfifoda_ctr.pre_map.hdb
.........\..\adfifoda_ctr.psp
.........\..\adfifoda_ctr.pss
.........\..\adfifoda_ctr.rpp.qmsg
.........\..\adfifoda_ctr.rtlv.hdb
.........\..\adfifoda_ctr.rtlv_sg.cdb
.........\..\adfifoda_ctr.rtlv_sg_swap.cdb
.........\..\adfifoda_ctr.sgate.rvd
.........\..\adfifoda_ctr.sgate_sm.rvd
.........\..\adfifoda_ctr.sgdiff.cdb
.........\..\adfifoda_ctr.sgdiff.hdb
.........\..\adfifoda_ctr.signalprobe.cdb
.........\..\adfifoda_ctr.sim.cvwf
.........\..\adfifoda_ctr.sim.hdb
.........\..\adfifoda_ctr.sim.qmsg
.........\..\adfifoda_ctr.sim.rdb
.........\..\adfifoda_ctr.sld_design_entry.sci
.........\..\adfifoda_ctr.sld_design_entry_dsc.sci
.........\..\adfifoda_ctr.syn_hier_info
.........\..\adfifoda_ctr.tan.qmsg
.........\..\adfifoda_ctr.tis_db_list.ddb
.........\..\altsyncram_79e1.tdf
.........\..\altsyncram_fpe1.tdf
.........\..\altsyncram_h6e1.tdf
.........\..\altsyncram_hm31.tdf
.........\..\altsyncram_jj31.tdf
.........\..\altsyncram_tj31.tdf
.........\..\altsyncram_vm31.tdf
.........\..\cntr_kkf.tdf
.........\..\prev_cmp_adfifoda_ctr.asm.qmsg
.........\..\prev_cmp_adfifoda_ctr.fit.qmsg
.........\..\prev_cmp_adfifoda_ctr.map.qmsg
.........\..\prev_cmp_adfifoda_ctr.qmsg
.........\..\prev_cmp_adfifoda_ctr.sim.qmsg
.........\..\prev_cmp_adfifoda_ctr.tan.qmsg
.........\..\shift_taps_15m.tdf
.........\..\shift_taps_b3m.tdf
.........\..\shift_taps_g3m.tdf
.........\..\shift_taps_q4m.tdf
.........\..\wed.wsf
.........\fifo.v
.........\fifo.v.bak
.........\fifo2.v
.........\fifo2_bb.v
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