Description: Serial DA FIR filter algorithm using 16 bands, directly available, VHDL programming
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [DA_FIR] - Based on Distributed algorithms realize
- [da_fir] - 8-order FIR filter symmetric coefficient
- [DA_fir] - Distributed algorithm based on FIR filte
- [vhdl] - FIR filter performance parameters The de
- [fir] - fir filter, Verilog language written in
- [Double_FPU] - Details of the format of double-precisio
- [FPGA-FIR] - FIR filter algorithm, using VHDL program
- [DA-FIR] - DA algorithm using FIR filter design pri
- [ad_da_ctr] - FPGA-based ad and da conversion Verilog
File list (Check if you may need any files):
da\adder_mac.v
..\ctrl_all.v
..\dacase8_1.v
..\dacase8_2.v
..\da_fir.prd
..\da_fir.prj
..\da_fir.qpf
..\DA_top.cr.mti
..\DA_top.mpf
..\DA_top.v
..\matlab_sim\fir_da.m
..\..........\fir_da_tb.m
..\..........\gencase.m
..\MUX_16X1_M.v
..\Q_258_0_15_0_.mif
..\Q_258_0_15_0_mif1.mif
..\readme.txt
..\..v_3\AutoConstraint_DA_top.sdc
..\.....\MUX_16X1_M.fse
..\.....\MUX_16X1_M.htm
..\.....\MUX_16X1_M.srd
..\.....\MUX_16X1_M.srm
..\.....\MUX_16X1_M.srr
..\.....\MUX_16X1_M.srs
..\.....\MUX_16X1_M.sxr
..\.....\MUX_16X1_M.tcl
..\.....\MUX_16X1_M.tlg
..\.....\MUX_16X1_M.vqm
..\.....\MUX_16X1_M.xrf
..\.....\MUX_16X1_M_cons.tcl
..\.....\MUX_16X1_M_rm.tcl
..\.....\Q_258_0_15_0_.mif
..\.....\Q_258_0_15_0_mif1.mif
..\.....\rpt_DA_top.areasrr
..\.....\rpt_DA_top_areasrr.htm
..\.....\syntmp\MUX_16X1_M.msg
..\.....\......\MUX_16X1_M.plg
..\.....\......\MUX_16X1_M_cons_ui.tcl
..\.....\......\MUX_16X1_M_flink.htm
..\.....\......\MUX_16X1_M_srr.htm
..\.....\......\MUX_16X1_M_toc.htm
..\.....\verif\MUX_16X1_M.vif
..\shift_ram.v
..\.im\adder_mac.v
..\...\ctrl_all.v
..\...\dacase8_1.v
..\...\dacase8_2.v
..\...\DA_top.v
..\...\DA_top_tb.v
..\...\imp_in.txt
..\...\MUX_16X1_M.v
..\...\shift_ram.v
..\veryclean.bat
..\work\@d@a_top\verilog.asm
..\....\........\_primary.dat
..\....\........\_primary.vhd
..\....\........_tb\verilog.asm
..\....\...........\_primary.dat
..\....\...........\_primary.vhd
..\....\.m@u@x_16@x1\verilog.asm
..\....\............\_primary.dat
..\....\............\_primary.vhd
..\....\adder_mac\verilog.asm
..\....\.........\_primary.dat
..\....\.........\_primary.vhd
..\....\ctrl_all\verilog.asm
..\....\........\_primary.dat
..\....\........\_primary.vhd
..\....\dacase8_1\verilog.asm
..\....\.........\_primary.dat
..\....\.........\_primary.vhd
..\....\........2\verilog.asm
..\....\.........\_primary.dat
..\....\.........\_primary.vhd
..\....\shift_ram\verilog.asm
..\....\.........\_primary.dat
..\....\.........\_primary.vhd
..\....\_info
..\rev_3\par_1
..\.....\syntmp
..\.....\verif
..\work\@d@a_top
..\....\@d@a_top_tb
..\....\@m@u@x_16@x1
..\....\adder_mac
..\....\ctrl_all
..\....\dacase8_1
..\....\dacase8_2
..\....\shift_ram
..\matlab_sim
..\rev_3
..\sim
..\work
da
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