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[Other resource] 异步FIFO存储器的控制设计

Description: 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Platform: | Size: 6655 | Author: 李鹏 | Hits:

[USB develop] USB and SDRAM Controller

Description: 基于CY7C68013A的Slave FIFO和SDRAM控制器
Platform: | Size: 10313628 | Author: xjtuzhangx@163.com | Hits:

[VHDL-FPGA-Verilog] 异步FIFO存储器的控制设计

Description: 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Platform: | Size: 6144 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] I2C_1.1

Description: Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo's---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack
Platform: | Size: 3072 | Author: 郑开科 | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
Platform: | Size: 5120 | Author: 陈晨 | Hits:

[VHDL-FPGA-Verilog] ethernet_vhdl

Description: 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
Platform: | Size: 30720 | Author: 王晶 | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[SCM] 20080402154056

Description: 可以用的ＥＺ－ＵＳＢ控制器ＳＬＡＶＥ　ＦＩＦＯ　Ｃ＋＋程序-Can use the EZ-USB controller SLAVE FIFO C program
Platform: | Size: 142336 | Author: sxn | Hits:

[Communication-Mobile] uart

Description: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Platform: | Size: 3072 | Author: duan | Hits:

[OS Develop] storagectrl

Description: 演示几种存储控制器的算法，fifo，lru，nur，opt-Demonstration of several storage controller algorithm, fifo, lru, nur, opt
Platform: | Size: 6144 | Author: ccl | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[Software Engineering] FIFO_design_reference_document

Description: FIFO设计的参考文档 Project name : Fifo -- Project description : Fifo controller Unit 工程名 : FIFO.VHD 用到库文件IEEE.STD_LOGIC_1164-FIFO reference design document Project name : Fifo -- Project description : Fifo controller Unit -- -- File name : FIFO.VHD -- Destination library : -- Dependencies : IEEE.STD_LOGIC_1164
Platform: | Size: 2048 | Author: mhb | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[VHDL-FPGA-Verilog] SDCard_Controller

Description: SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Platform: | Size: 24576 | Author: xiafei | Hits:

[VHDL-FPGA-Verilog] arlut_fifo_interface

Description: fifo控制器，可以加到nios系统下，通过nios进行FIFO的读写，经过本人的项目验证-fifo controller, can be added to the nios system, through the nios to FIFO read and write, after I verified the project
Platform: | Size: 16384 | Author: 11 | Hits:

[VHDL-FPGA-Verilog] VGA-Controller

Description: FPGA do vga display controller. achieve include: fifo mem, vga core, rgb controller,
Platform: | Size: 7168 | Author: Aleks | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
Platform: | Size: 110592 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] FIFO-Controller-with-LFSR

Description: FIFO Controller With LFSR
Platform: | Size: 3072 | Author: hadimk | Hits:

[VHDL-FPGA-Verilog] fifo_controller

Description: 用verilog语言实现FIFO控制器，控制FIFO的读写过程，有空满标志(Implementing the FIFO controller)
Platform: | Size: 84992 | Author: 牛啊你 | Hits:
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