Description: This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
- [statemachine11.2] - recommend downloading Verilog state mach
- [uart-verilog-vhdl] - with vhdl and verilog prepared by the se
- [VHDL_to_UART] - A serial communication program written w
- [uart1] - Serial port program, based on VHDL, very
- [COMM] - In the DOS environment, UART serial port
- [UART] - Input clock 20M, the baud rate for 9600,
- [gh_uart_16550_080407] - Commonly used in FPGA development serial
- [UART] - Contain complete UART code, including se
- [FPGA_VHDL_code] - FPGA to learn very valuable information,
- [UART_spec] - a UART model with FIFO buffer, design wi
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