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Title: UART_spec Download
 Description: a UART model with FIFO buffer, design with verilog
  • [FIFO_v] - FIFO verilog achieve, enclosing testbenc
  • [S7_UART] - FPGA realization of the use of serial co
  • [uart] - This is the UART controller, has been ru
  • [UART] - The use of FPGA-FIFO, state machine, pin
  • [mini-uart] - Verilog implementation mini-uart, code F
  • [UART] - I have written of the FPGA asynchronous
  • [fifo-verilog] - Own design of a FIFO register, with veri
File list (Check if you may need any files):
UART_spec.pdf
    

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