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[Other resource] FIFO_Syn

Description: 同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合
Platform: | Size: 26159 | Author: shenyunfei | Hits:

[Other resource] 4VerilogFIFO

Description: 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合
Platform: | Size: 2793 | Author: shenyunfei | Hits:

[Other resource] FIFO-DC

Description: FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合
Platform: | Size: 60930 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] FIFO_Syn

Description:
Platform: | Size: 25600 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] 4VerilogFIFO

Description: 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 2048 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] FIFO-DC

Description: FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合-FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC
Platform: | Size: 60416 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] zzmodelsim

Description: verilog仿真工具modelsim的使用教程,幻灯片形式的,图文并茂,简单易学.经典的老教材-ModelSim Verilog simulation tool use tutorials, slide the form of illustrations, easy to learn. classic old material
Platform: | Size: 505856 | Author: oasis | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Platform: | Size: 31744 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 高性能设计中常用的fifo模型，采用单端读取数据的方式，数据的位宽以及fifo的深度可以设置。通过modelsim仿真-Fifo design commonly used in high-performance models, using single-ended way to read data, the data bit width and the depth of the fifo can be set. Modelsim simulation by
Platform: | Size: 19456 | Author: megamus | Hits:

[VHDL-FPGA-Verilog] fifo_syn

Description: 同步fifo，有测试向量，用modelsim仿真验证通过。-Synchronous fifo, there are test vectors, by using modelsim simulation.
Platform: | Size: 60416 | Author: 曹蒙蒙 | Hits:

[VHDL-FPGA-Verilog] 3fifo_fifo

Description: 程序实现了FPGA内部FIFO之间的数据传输。已通过modelsim调试！-Procedures to achieve the data transmission between the FPGA internal FIFO. Modelsim has passed debugging!
Platform: | Size: 9124864 | Author: 袁官福 | Hits:

[VHDL-FPGA-Verilog] ram_fifo_ram

Description: 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
Platform: | Size: 8185856 | Author: 袁官福 | Hits:

[VHDL-FPGA-Verilog] FIFO_TD

Description: FIFO的VHDL测试程序,在Modelsim下完全可以运行-The test_bench of fifo
Platform: | Size: 2048 | Author: 三木 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 本文档是一个异步FIFO设计的完整工程，利用modelsim仿真软件，分不同的模块-This document is the complete works of an asynchronous FIFO design, the use of the modelsim simulation software, divided into different modules
Platform: | Size: 504832 | Author: yanjiajun | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
Platform: | Size: 6605824 | Author: xiadafang | Hits:

[VHDL-FPGA-Verilog] fifo2

Description: 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
Platform: | Size: 4096 | Author: T~T | Hits:

[Other Embeded program] FIFO1

Description: 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据　(FIFO的宽度：也就是英文资料里常看到的THE  WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以存储8个8位的数据，深度为12，就可以存储12个8位的数据。)-Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.)
Platform: | Size: 33792 | Author: 江燕子 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
Platform: | Size: 135168 | Author: seer | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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