Search - filter design using vhdl

[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[VHDL-FPGA-Verilog] CICFPGA

Description: 本文总结了CIC 滤波器理论要点，介绍了采用FPGA设计CIC 滤波器的基本方法，使滤波器的参数可以按实际需要任意更改，给出了仿真结，验证了设计的可靠性和可行性。采用该方法设计的CIC 滤波器已用于DDC芯片，也适合下一代高频雷达系统的要求。-This paper summarizes the main points of CIC filter theory, introduced the CIC filter design using FPGA basic ways in which filter parameters can be arbitrary according to the actual needs change, the simulation node to verify the reliability of the design and feasibility. Designed using the CIC filter has been used in DDC chips, also suitable for the next generation of high-frequency radar system requirements.
Platform: | Size: 700416 | Author: 会飞的鱼 | Hits:

[Documents] IIRfilterFPGA

Description: 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules of the design method and device using VHDL and FPGA implementation of IIR digital filter.
Platform: | Size: 661504 | Author: 杨培科 | Hits:

[Software Engineering] VHDL_FPGA_FILTER

Description: 用VHDL语言设计基于FPGA器件的高采样率FIR滤波器,基于VHDL与CPLD器件的FIR数字滤波器的设计-Design using VHDL language FPGA devices based on high sampling rate FIR filter, based on VHDL and CPLD devices, the design of FIR digital filter
Platform: | Size: 913408 | Author: 玉玲 | Hits:

[VHDL-FPGA-Verilog] multiratefilterdesign

Description: 自己编写多速率滤波器设计，采用VHDL语言，通过FPGA实现-I have written multi-rate filter design using VHDL language, through the FPGA to achieve
Platform: | Size: 161792 | Author: 球球jk | Hits:

[VHDL-FPGA-Verilog] CIC_DEC_4

Description: CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
Platform: | Size: 1024 | Author: 42200306 | Hits:

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

Description: FIR filter design method using Xilinx FPGA platform.
Platform: | Size: 1805312 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] fir_liujiao

Description: 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
Platform: | Size: 96256 | Author: juan | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir filter design using vhdl codes
Platform: | Size: 1024 | Author: gowtham | Hits:

[Other Embeded program] vhdl

Description: there is Design a butterworth low pass IIR filter. (a) Using butterworth to design an IIR low pass filter with Fs=8192hz and Fpass =1000 and Fstop =1200. You use the minimum order of filter. And match exactly at pass band. and other programs
Platform: | Size: 2048 | Author: fathima | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[Other] a2

Description: 用MATLAB设计及FPGA实现IIR滤波器的方法摘要本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。-Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.
Platform: | Size: 2021376 | Author: sfef | Hits:

[source in ebook] eda

Description: 利用vhdl设计fir滤波器，有完整程序，包含加法器，乘法器。-Design using vhdl fir filter, a complete program, including adders, multipliers.
Platform: | Size: 186368 | Author: 黄林 | Hits:

[VHDL-FPGA-Verilog] FIR-filter-using-fpga-design

Description: 基于FPGA的高阶FIR滤波器设计4有matlab设计步骤 4.3更详细第六章量化系数实例-FIR using FPGA ，QuartusII software
Platform: | Size: 4539392 | Author: 星空心晴之夏 | Hits:

[VHDL-FPGA-Verilog] filter1

Description: 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hope it would be useful
Platform: | Size: 13312 | Author: 万勇 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
Platform: | Size: 4126720 | Author: 翁萍 | Hits:

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

Description: ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.
Platform: | Size: 379904 | Author: phitoan | Hits:

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[Button control] 4yue11haoxiawu

[VHDL-FPGA-Verilog] CICFPGA

[Documents] IIRfilterFPGA

[Software Engineering] VHDL_FPGA_FILTER

[VHDL-FPGA-Verilog] multiratefilterdesign

[VHDL-FPGA-Verilog] CIC_DEC_4

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

[VHDL-FPGA-Verilog] fir_liujiao

[VHDL-FPGA-Verilog] FIR

[Other Embeded program] vhdl

[VHDL-FPGA-Verilog] fir

[Other] a2

[source in ebook] eda

[VHDL-FPGA-Verilog] FIR-filter-using-fpga-design

[VHDL-FPGA-Verilog] filter1

[VHDL-FPGA-Verilog] FIR

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

[VHDL-FPGA-Verilog] FIR

[VHDL-FPGA-Verilog] Adaptive-digital-filter

[VHDL-FPGA-Verilog] filter_VHDL

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