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[Embeded-SCM Develop] first_nios2_system_sim

Description: nios 环境下的软件编程，主要用来设计cpu内核-nios environment of software programming, mainly for the design of core cpu
Platform: | Size: 2048 | Author: | Hits:

[matlab] fir_core

Description: fir滤波器，用matlab，dsp和quartus2设计的-fir filter, using Matlab, dsp design and quartus2
Platform: | Size: 95232 | Author: 吴涛 | Hits:

[DSP program] fir

Description: dsp的fir滤波的核心汇编程序，在ccs集成开发环境中运行调试通过 。-dsp core of the fir filter assembler in ccs integrated development environment to run through the debugger.
Platform: | Size: 13312 | Author: 黄黄 | Hits:

[VHDL-FPGA-Verilog] kcpsm3

Description: picoblaze xilinx的8位处理器核和他的编译器。能嵌放到FGPA中-picoblaze xilinx 8-bit processor core, and his compiler. Can be embedded into FGPA in
Platform: | Size: 57344 | Author: 徐云龙 | Hits:

[VHDL-FPGA-Verilog] FIR_TEST

Description: 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块，并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we design such core modules as CIC filter, HB filter and FIR filter of the digital down converter.
Platform: | Size: 182272 | Author: 邓建良 | Hits:

[Mathimatics-Numerical algorithms] exp02_cpuFIR

Description: 在DSP上实现的FIR的COU核心代码，可以顺利完成此FIR的滤波器功能-In the DSP to achieve the COU the FIR core code, the successful completion of the FIR filter function
Platform: | Size: 68608 | Author: 夏礼吉 | Hits:

[Mathimatics-Numerical algorithms] exp03_cpuIIR

Description: 在DSP上实现的IIR的CPU核心代码，可以顺利完成此FIR的滤波器功能-In the DSP to achieve the IIR of the CPU core code, the successful completion of the FIR filter function
Platform: | Size: 74752 | Author: 夏礼吉 | Hits:

[DSP program] myfir

Description: 利用fir滤波器ip-core设计滤波器，数据为16bit，速率为61.44mhz，工作时钟为245.76mhz-The use of fir filter ip-core design of filters, the data for the 16bit, rate 61.44mhz, working clock 245.76mhz
Platform: | Size: 1024 | Author: 王丽 | Hits:

[Software Engineering] xiabianpin

Description: 文中应用软件无线电思想对数字下变频器中的几个关键技术进行了研究,对下变频各个模块所涉及到的CIC、HB、FIR等关键算法进行了讨论、提炼与总结,应用matlab软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块,并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真.仿真结果表明,系统实现了对中频信号的下变频处理且无失真现象,大大减少了软件无线电系统数宁信号处理的运算量和数据的存储量,极大地提高了系统的实时性.-The paper application software radio digital down converter in the thinking of several key technologies have been studied for the next conversion involved in each module to the CIC, HB, FIR and other key algorithms were discussed, refined and summarized the application of matlab software design downconverter in the CIC, HB, FIR filters and other core modules, and integration of various modules from the software point of complete structures and functions of the system simulation. The simulation results show that the system achieved the right under the IF signal Frequency processing and without distortion, thus greatly reducing the number of software-defined radio system, rather the amount of signal processing operations and data storage capacity, greatly improve the system in real time.
Platform: | Size: 287744 | Author: 王楚宏 | Hits:

[DSP program] bf_fir

Description: Blackfin处理器的FIR滤波器函数。应用程序以C编写，核心代码以汇编编写，效率极高-Blackfin processor, FIR filter function. Application to C written in the core code to compile written in highly efficient
Platform: | Size: 45056 | Author: hu | Hits:

[Other] FIRTest

Description: Remez算法求滤波器冲击响应系数--最佳FIR数字滤波器核心算法-Remez algorithm to solve the filter impulse response coefficients- the core algorithm for FIR digital filter design.
Platform: | Size: 258048 | Author: | Hits:

[matlab] pso

Description: 滤波器设计是信号处理的核心问题之一,Matlab软件在多个研究领域都有着广泛的应用。 本文介绍了基于Matlab环境下,用窗函数设计法实现FIR数字滤波器的设计,并阐述了与以前人 们常用的设计方法的区别,给出了设计实例。仿真结果表明,设计结果的各项性能指标均达到指定 要求,且设计过程简便易行。 -The design of filters is a core problem in signal processing. MATLAB software iswidely used inmany research fields. This article introduces themethod ofusingwindow function to design FIR digital filters based onMATLAB and its differences from the tradi- tional designmethods. And itgives a design example. The simulation shows that the design results canmeet the requirements verywell and the design procedure is very simple and practica.l
Platform: | Size: 77824 | Author: xiaoxiao | Hits:

[Software Engineering] ISE_IP_FIR_FPGA

Description: 利用ISE的IP核在FPGA上设计fir滤波器-Fir filter IP core on FPGA design using the ISE
Platform: | Size: 101376 | Author: ACER | Hits:

[VHDL-FPGA-Verilog] signal-fir

Description: FPGA实现FIR滤波器，对信号的滤波处理，其中I用IP核实现数据的存储核-Based on the IP core of FPG, realize FIR filter design
Platform: | Size: 196608 | Author: 赵龙贺 | Hits:

[VHDL-FPGA-Verilog] COSTAS_LOOP

Description: 使用ISE12.1编写的Costas环，用于载波恢复，直接使用了IP核中的FIR和DDS模块-Use ISE12.1 written Costas loop for carrier recovery, the direct use of the IP core of FIR and DDS module
Platform: | Size: 1024 | Author: nike | Hits:

[VHDL-FPGA-Verilog] fir_test01

Description: 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
Platform: | Size: 1510400 | Author: xuegamgma | Hits:

[Software Engineering] Filter-by-using-DSP-Lib

Description: stm32 cortex-m4的dsp库，包括各种滤波算法，例如FIR、IIR以及FFT等-dsp library of stm32 with cortex-m4 core which includes varies of algorithm like fir/IIR and fft etc
Platform: | Size: 173056 | Author: 邓泽林 | Hits:

[VHDL-FPGA-Verilog] 20140825

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 5541888 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 6000640 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] FIR设计实现sgh

Description: FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Platform: | Size: 25600 | Author: 韩冻少 | Hits:
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