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[Other resource] fir_using_FPGA

Description: 基于verilog的fir滤波，并带matlab仿真
Platform: | Size: 24408 | Author: 宇天 | Hits:

[VHDL-FPGA-Verilog] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26624 | Author: QQ | Hits:

[VHDL-FPGA-Verilog] fir_using_FPGA

Description: 基于verilog的fir滤波，并带matlab仿真-Verilog-based filtering of fir and bring matlab simulation
Platform: | Size: 24576 | Author: 宇天 | Hits:

[Communication-Mobile] DDC

Description: 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR-DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
Platform: | Size: 2048 | Author: yeong | Hits:

[VHDL-FPGA-Verilog] base_fir

Description: 使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
Platform: | Size: 21504 | Author: xiaoLEE | Hits:

[VHDL-FPGA-Verilog] fir_hdl

Description: 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。-Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
Platform: | Size: 97280 | Author: wei | Hits:

[DSP program] dspddc_R12p1

Description: 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
Platform: | Size: 17408 | Author: 郑程 | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] Xilinx-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Platform: | Size: 3090432 | Author: 胡文静 | Hits:

[VHDL-FPGA-Verilog] fir_PGA

Description: 一种基于verilog的fir滤波源码，并带matlab仿真源程序。-Based on the fir filter verilog source code and source code with matlab simulation.
Platform: | Size: 23552 | Author: 对称 | Hits:

[VHDL-FPGA-Verilog] FIR_matlab_verilog

Description: matlab 仿真低通滤波器，然后用verilog硬件实现-using matlab to simulate a fir lowpass, then using verilog to implement it.
Platform: | Size: 3072 | Author: Fengxiaodong | Hits:

[Other] da_fir

Description: 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） ​ 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。​ 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(Finite Impulse Response, FIR)。由于FIR滤波器在实现上主要是完成乘累加MAC的功能，采用传统MAC算法设计FIR滤波器将消耗大量硬件资源。而采用分布式算法 (Distributed Arithmetic, DA)，将MAC运算转化为查找表(Look-Up-Table, LUT)输出，不仅能在硬件规模上得到改善，而且更易通过实现流水线设计来提高速度。因此本文采用分布式算法设计一个可配置的FIR滤波器，并以31阶的低通FIR滤波器为例说明分布式算法滤波器结构。- FPGA verilog
Platform: | Size: 6144 | Author: 石康 | Hits:

[VHDL-FPGA-Verilog] matlab-and-verilog-fir4_3

Description: 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
Platform: | Size: 8192 | Author: 李静 | Hits:

[VHDL-FPGA-Verilog] fir_verilog_matlab

Description: 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.
Platform: | Size: 1352704 | Author: 郭婷 | Hits:

[VHDL-FPGA-Verilog] firfilterPfpga

Description: FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
Platform: | Size: 9401344 | Author: dfdqzp | Hits:

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