Search - fir xilinx

[VHDL-FPGA-Verilog] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228352 | Author: yaoming | Hits:

[matlab] fir_core

Description: fir滤波器，用matlab，dsp和quartus2设计的-fir filter, using Matlab, dsp design and quartus2
Platform: | Size: 95232 | Author: 吴涛 | Hits:

[Streaming Mpeg4] dsp48macro_macfir

Description: xilinx embedded system: FIR design example.
Platform: | Size: 29696 | Author: ylwang | Hits:

[VHDL-FPGA-Verilog] kcpsm3

Description: picoblaze xilinx的8位处理器核和他的编译器。能嵌放到FGPA中-picoblaze xilinx 8-bit processor core, and his compiler. Can be embedded into FGPA in
Platform: | Size: 57344 | Author: 徐云龙 | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[matlab] filter

Description: 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
Platform: | Size: 268288 | Author: xueanxi | Hits:

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

Description: FIR filter design method using Xilinx FPGA platform.
Platform: | Size: 1805312 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] reload_fir

Description: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Platform: | Size: 16727040 | Author: 林寒风 | Hits:

[VHDL-FPGA-Verilog] Xilinx-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Platform: | Size: 3090432 | Author: 胡文静 | Hits:

[Other] FIR

Description: 这是一个在MATLAB上编写的FIR滤波器程序，并能被AccelDSP综合，下载到Xilinx上进行硬件仿真，适合对AccleDSP学习的人应用-This is a MATLAB program to write the FIR filter, and can be integrated AccelDSP downloaded to the Xilinx on hardware simulation, suitable for application on AccleDSP learn,
Platform: | Size: 880640 | Author: qiwen | Hits:

[VHDL-FPGA-Verilog] fir

Description: 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
Platform: | Size: 470016 | Author: chenlan | Hits:

[VHDL-FPGA-Verilog] 61i_reloadable_da_fir_v8_0_vhdl_ise

Description: FIR Filter+Xilinx ISE
Platform: | Size: 96256 | Author: rocky | Hits:

[ELanguage] fir-mat

Description: filtro pasabajos para hdl xilinx coeficientes positivos
Platform: | Size: 520192 | Author: btaivan | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 使用Verilog语言编写的FIR滤波器,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog
Platform: | Size: 8192 | Author: 于洋 | Hits:

[Other] Xilinx-FIRfilter-iP

Description: Xilinx IP核设计FIR滤波器,调用IP核实现FIR滤波器，相关具体步骤还有Verilog HDL的相关代码-verilog HDL
Platform: | Size: 346112 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] FPGA-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码
Platform: | Size: 3090432 | Author: 楚轩 | Hits:

[Other] fir

Description: A classic FIR filter implemented using Verilog HDL on the Xilinx software-A classic FIR filter implemented using Verilog HDL on the Xilinx software
Platform: | Size: 1024 | Author: DarkRofl | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR filter in verilog for xilinx ise design suit
Platform: | Size: 190464 | Author: addy007 | Hits:

[Other] E4_6_FirIpCore

Description: 用vhdl语言在xilinx上用ip核实现的fir滤波器的设计(Design of FIR filter implemented with IP kernel on Xilinx in VHDL language)
Platform: | Size: 1198080 | Author: cc12 | Hits:

[Other] VHDL-FIR-filters

Description: ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has been synthesized with Xilinx Vivado 2015.1 to confirm the correct DSP cascade chain is inferred.
Platform: | Size: 37888 | Author: Abkoti | Hits:

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[VHDL-FPGA-Verilog] firfpga

[matlab] fir_core

[Streaming Mpeg4] dsp48macro_macfir

[VHDL-FPGA-Verilog] kcpsm3

[Linux-Unix] Linux_bc

[matlab] filter

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

[VHDL-FPGA-Verilog] reload_fir

[VHDL-FPGA-Verilog] Xilinx-FIR

[Other] FIR

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] 61i_reloadable_da_fir_v8_0_vhdl_ise

[ELanguage] fir-mat

[VHDL-FPGA-Verilog] FIR

[Other] Xilinx-FIRfilter-iP

[VHDL-FPGA-Verilog] FPGA-FIR

[Other] fir

[VHDL-FPGA-Verilog] FIR

[Other] E4_6_FirIpCore

[Other] VHDL-FIR-filters

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