Search - floating point adder in vhdl

[VHDL-FPGA-Verilog] floating_point_adder

Description: 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
Platform: | Size: 1024 | Author: 钟毓秀 | Hits:

[Windows Develop] fpadd

Description: Floating point adder
Platform: | Size: 10240 | Author: Shani Kumar Goutam | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] fpufiles

Description: floating point adder mul and sub in verilog code
Platform: | Size: 19456 | Author: khosro raja | Hits:

[VHDL-FPGA-Verilog] floating-point-adder-subtractor

Description: floating point adder/subtractor in VHDL
Platform: | Size: 3072 | Author: abeymohammed | Hits:

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[VHDL-FPGA-Verilog] floating_point_adder

[Windows Develop] fpadd

[VHDL-FPGA-Verilog] Floating-Point-Adder

[VHDL-FPGA-Verilog] fpufiles

[VHDL-FPGA-Verilog] floating-point-adder-subtractor

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