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[VHDL-FPGA-Verilog] vhdldesign

Description: 浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Platform: | Size: 202752 | Author: yan | Hits:

[VHDL-FPGA-Verilog] floating_point_adder

Description: 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
Platform: | Size: 1024 | Author: 钟毓秀 | Hits:

[VHDL-FPGA-Verilog] fpufiles

Description: floating point adder mul and sub in verilog code
Platform: | Size: 19456 | Author: khosro raja | Hits:

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