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[Other resource] 单片机子程序库

Description: 用单片机汇编语言写的使用的子程序 包扩浮点书的加减还有 模糊算法-SCM assembly language used to write the use of the subroutine package expanding the floating-point addition and subtraction algorithm still fuzzy
Platform: | Size: 21070 | Author: 高峰 | Hits:

[Other resource] flowadd

Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Platform: | Size: 1442 | Author: 张桓铭 | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Platform: | Size: 1024 | Author: 张桓铭 | Hits:

[SCM] 51单片机汇编葵花宝典

Description: 各种51单片机源程序集，包括浮点数的计算，多字节的加减等算法的实现-SCM source scripts, including floating point calculations, multi-byte such as addition and subtraction algorithm implementation
Platform: | Size: 125952 | Author: 周云 | Hits:

[SCM] 单片机子程序库

Description: 用单片机汇编语言写的使用的子程序 包扩浮点书的加减还有 模糊算法-SCM assembly language used to write the use of the subroutine package expanding the floating-point addition and subtraction algorithm still fuzzy
Platform: | Size: 20480 | Author: 高峰 | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。-Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.
Platform: | Size: 16384 | Author: WeimuMa | Hits:

[MPI] floatmul

Description: 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Platform: | Size: 1024 | Author: NOVEI | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
Platform: | Size: 1024 | Author: 蔡大 | Hits:

[SCM] asm51

Description: 51子程序库，浮点、定点、加法、减法、乘法、除法-51 subroutine library, floating point, fixed point, addition, subtraction, multiplication, division
Platform: | Size: 33792 | Author: 张燕 | Hits:

[Windows Develop] Test_Float_Peak

Description: 用c编写的用于测试浮点运算峰值的小程序。采用长度为N的浮点数组source[]自身相加N次的方法进行N*N次浮点加法运算来测试浮点加法峰值。-With c prepared for testing small peak floating-point operations procedures. Length of the floating-point numbers for the N group source [] the sum of N times its own methods of N* N floating-point addition operations to test the peak floating-point adder.
Platform: | Size: 963584 | Author: 小华 | Hits:

[VHDL-FPGA-Verilog] pre_norm_div

Description: 一种用VHDL语言描述的浮点除前规格化的源代码编程-VHDL language used to describe a floating-point addition to the source code before the standardized programming
Platform: | Size: 2048 | Author: zhshup | Hits:

[VHDL-FPGA-Verilog] post_norm_addsub

Description: 浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful
Platform: | Size: 3072 | Author: zhshup | Hits:

[Data structs] calculator

Description: 科学计算器。可以解读表达式，进行整数、浮点数的加减乘除运算。-Scientific calculator. Expression can be interpreted, for integer, floating-point addition and subtraction, multiplication and division calculations.
Platform: | Size: 2048 | Author: 晴天雨 | Hits:

[Windows Develop] adderenv

Description: 产生浮点加法运算单元的测试激励及期望输出-Floating-point addition operations generate unit test incentives and the desired output
Platform: | Size: 5120 | Author: 孟军 | Hits:

[VHDL-FPGA-Verilog] fudianshuyunsuan

Description: 介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
Platform: | Size: 323584 | Author: jiachen | Hits:

[matlab] jisuanjizuchnegyuanli

Description: 能够实现定点小数的机器数表示、定点小数的变形补码加减运算、定点小数的原码一位乘法运算和浮点数的加减运算。-Able to achieve fixed-point decimal number of machines that the deformation of complement fixed-point decimal addition and subtraction operations, the original code a fixed-point decimal multiplication and floating-point operations of addition and subtraction.
Platform: | Size: 356352 | Author: 施振磊 | Hits:

[VHDL-FPGA-Verilog] floating_point_addition_subtraction

Description: Simple floating point addition unit written in Verilog
Platform: | Size: 3072 | Author: binh | Hits:

[JSP/Java] Calculator

Description: 建议计算器，能进行浮点数的加减乘除，swing界面-Recommended calculator for floating-point addition and subtraction, multiplication and division can, swing interface
Platform: | Size: 140288 | Author: strive4future | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[Other] vhdl-ALU-floating-point-single-precision

Description: Arithmetic and logic unit for floating point single precision addition/substruction, multiplication, division and square root.
Platform: | Size: 10240 | Author: RACHIDI | Hits:
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