Search - floating point multiplier

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[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Update : 2025-02-17 Size : 175kb Publisher : 李中伟
[Books] 32bits_float_muliplier DL : 0: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Update : 2025-02-17 Size : 95kb Publisher : downloader
[VHDL-FPGA-Verilog] cf_fp_mul DL : 0: 浮点型的乘法器,采用VHDL语言描述浮点型的乘法器,文中包含测试文件-Floating-point type multiplier using VHDL language to describe the type floating-point multiplier, the text included in the test document
Update : 2025-02-17 Size : 671kb Publisher : asdtgg
[VHDL-FPGA-Verilog] 1 DL : 0: 高效结构的多输入浮点乘法器在FPGA上的实现-Efficient structure of multi-input floating-point multiplier in FPGA Implementation
Update : 2025-02-17 Size : 137kb Publisher : stormy
[VHDL-FPGA-Verilog] multiply DL : 1: 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
Update : 2025-02-17 Size : 1kb Publisher : gulu
[VHDL-FPGA-Verilog] fadd DL : 0: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Update : 2025-02-17 Size : 2kb Publisher : 兰兰
[Algorithm] multiply DL : 0: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Update : 2025-02-17 Size : 4kb Publisher : lanty
[Other] mux8 DL : 0: 定点八位乘法器的原理图设计，已通过功能仿真！-8 fixed-point multiplier schematic design, functional simulation has passed!
Update : 2025-02-17 Size : 403kb Publisher : lxp
[VHDL-FPGA-Verilog] FinalFPMultiplier DL : 0: Simple 32 bit Floating point Multiplier
Update : 2025-02-17 Size : 7.03mb Publisher : Rahul
[VHDL-FPGA-Verilog] floating_multi DL : 0: Floating point multiplier
Update : 2025-02-17 Size : 1.7mb Publisher : Alam
[Other] mult DL : 0: floating point multiplier
Update : 2025-02-17 Size : 2kb Publisher : prashanthi
[VHDL-FPGA-Verilog] fpu_v19 DL : 0: Floating Point Multiplier in VHDL
Update : 2025-02-17 Size : 335kb Publisher : shanmuga raja
[Software Engineering] doublemult DL : 0: 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确并对FPGA 实现的时序结果进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm for BOO TH generate part of the plot, with a mixed array and a tree structure to achieve the sum of the partial product, while also using a fast rounding algorithm to improve the performance of multipliers. The design of the multiplier is divided into four lines, carried out a simulation using FPGA verification result is correct and FPGA timing to achieve the results analyzed.
Update : 2025-02-17 Size : 205kb Publisher : terry
[VHDL-FPGA-Verilog] CourseDesign DL : 0: 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
Update : 2025-02-17 Size : 240kb Publisher : 李伟彬
[VHDL-FPGA-Verilog] floating-point-multiplier DL : 0: verilog implementation of the floating point multiplier
Update : 2025-02-17 Size : 1kb Publisher : ramtin
[VHDL-FPGA-Verilog] mult DL : 1: 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
Update : 2025-02-17 Size : 2kb Publisher : yolin
[VHDL-FPGA-Verilog] Floating-Point-Multiplier-in-Verilog DL : 0: Floating Point Multiplier in Verilog
Update : 2025-02-17 Size : 63kb Publisher : Khalid Nawaz Khan
[VHDL-FPGA-Verilog] floating-point-multiplier DL : 0: floating point multiplier in VHDL
Update : 2025-02-17 Size : 2kb Publisher : abeymohammed
[VHDL-FPGA-Verilog] floating-point-multip DL : 0: verilog code for floating point multiplier
Update : 2025-02-17 Size : 50kb Publisher : rajesh
[Other] Fixed-Floating-Point-Adder-Multiplier-master DL : 0: Fixed-Floating-Point-Adder-Multiplier with test bench
Update : 2025-02-17 Size : 9kb Publisher : liki20

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