Search - floating point multiplier in vhdl

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[Other resource] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
Update : 2008-10-13 Size : 175.34kb Publisher : 李中伟
[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Update : 2025-04-04 Size : 175kb Publisher : 李中伟
[VHDL-FPGA-Verilog] cf_fp_mul DL : 0: 浮点型的乘法器,采用VHDL语言描述浮点型的乘法器,文中包含测试文件-Floating-point type multiplier using VHDL language to describe the type floating-point multiplier, the text included in the test document
Update : 2025-04-04 Size : 671kb Publisher : asdtgg
[VHDL-FPGA-Verilog] 1 DL : 0: 高效结构的多输入浮点乘法器在FPGA上的实现-Efficient structure of multi-input floating-point multiplier in FPGA Implementation
Update : 2025-04-04 Size : 137kb Publisher : stormy
[Other] mux8 DL : 0: 定点八位乘法器的原理图设计，已通过功能仿真！-8 fixed-point multiplier schematic design, functional simulation has passed!
Update : 2025-04-04 Size : 403kb Publisher : lxp
[VHDL-FPGA-Verilog] floating_multi DL : 0: Floating point multiplier
Update : 2025-04-04 Size : 1.7mb Publisher : Alam
[VHDL-FPGA-Verilog] fpu_v19 DL : 0: Floating Point Multiplier in VHDL
Update : 2025-04-04 Size : 335kb Publisher : shanmuga raja
[VHDL-FPGA-Verilog] fpu_double_latest.tar DL : 0: floating point multiplier unit developed in vhdl
Update : 2025-04-04 Size : 226kb Publisher : challu
[VHDL-FPGA-Verilog] floating-point-multiplier DL : 0: floating point multiplier in VHDL
Update : 2025-04-04 Size : 2kb Publisher : abeymohammed