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[Other resource] vdevice

Description: 基于FPGA系统的数字电压表设计大范围，超精确的详细报告，共有40多页-FPGA-based system design digital voltage meter large-scale and ultra-precise details of the report, a total of over 40 pages
Platform: | Size: 140272 | Author: 刘嵘 | Hits:

[Other resource] DEMO1_KEY_LED

Description: KX_DVP3F型FPGA应用板/开发板（全套）包括：  CycloneII系列FPGA EP2C8Q208C8 40万们，含20M-270MHz锁相环2个。  RS232串行接口；VGA视频口  高速SRAM 512KB。可用于语音处理，NiosII运行等。  配置Flash EPCS2， 10万次烧写周期 。  isp单片机T89S8253：MCS51兼容单片机，12KB在系统可编程Flash ROM，10万次烧 写周期；2KB在系统可编程EEPROM，10万次烧写周期；2.7V-5.5V工作电压；0-24MHz 工作时钟；  2数码管显示器、20MHz时钟源（可通过FPGA中的锁相环倍频）；  液晶显示屏（20字X4行）；  工作电源5V、3.3V、1.2V混合电压源，良好电磁兼容性主板。  配套示例程序、资料、编程软件光盘等。  4X4键盘，4普通按键，8可锁按键，8发光管  BlasterMV编程下载器和并口通信线，可完成FPGA编程下载和isp单片机的编程。KX_DV3F开发板的源程序
Platform: | Size: 360723 | Author: ldg | Hits:

[VHDL-FPGA-Verilog] vdevice

Description: 基于FPGA系统的数字电压表设计大范围，超精确的详细报告，共有40多页-FPGA-based system design digital voltage meter large-scale and ultra-precise details of the report, a total of over 40 pages
Platform: | Size: 140288 | Author: 刘嵘 | Hits:

[VHDL-FPGA-Verilog] DEMO1_KEY_LED

Description: KX_DVP3F型FPGA应用板/开发板（全套）包括：  CycloneII系列FPGA EP2C8Q208C8 40万们，含20M-270MHz锁相环2个。  RS232串行接口；VGA视频口  高速SRAM 512KB。可用于语音处理，NiosII运行等。  配置Flash EPCS2， 10万次烧写周期 。  isp单片机T89S8253：MCS51兼容单片机，12KB在系统可编程Flash ROM，10万次烧 写周期；2KB在系统可编程EEPROM，10万次烧写周期；2.7V-5.5V工作电压；0-24MHz 工作时钟；  2数码管显示器、20MHz时钟源（可通过FPGA中的锁相环倍频）；  液晶显示屏（20字X4行）；  工作电源5V、3.3V、1.2V混合电压源，良好电磁兼容性主板。  配套示例程序、资料、编程软件光盘等。  4X4键盘，4普通按键，8可锁按键，8发光管  BlasterMV编程下载器和并口通信线，可完成FPGA编程下载和isp单片机的编程。KX_DV3F开发板的源程序-err
Platform: | Size: 360448 | Author: ldg | Hits:

[VHDL-FPGA-Verilog] jpeg.tar

Description: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
Platform: | Size: 3416064 | Author: Bill Guan | Hits:

[VHDL-FPGA-Verilog] cd4000x

Description: CD4000 双3输入端或非门+单非门 TI 　　CD4001 四2输入端或非门 HIT/NSC/TI/GOL 　　 双4输入端或非门 NSC 　　CD4006 18位串入/串出移位寄存器 NSC 　　CD4007 双互补对加反相器 NSC 　　CD4008 4位超前进位全加器 NSC 　　CD4009 六反相缓冲/变换器 NSC 　　CD4010 六同相缓冲/变换器 NSC 　　CD4011 四2输入端与非门 HIT/TI 　　CD4012 双4输入端与非门 NSC 　　CD4013 双主-从D型触发器 FSC/NSC/TOS 　　CD4014 8位串入/并入-串出移位寄存器 NSC 　　CD4015 双4位串入/并出移位寄存器 TI 　　CD4016 四传输门 FSC/TI 　　CD4017 十进制计数/分配器 FSC/TI/MOT 　　CD4018 可预制1/N计数器 NSC/MOT -CD4000-cd4066
Platform: | Size: 2422784 | Author: 徐科峰 | Hits:

[VHDL-FPGA-Verilog] jtagdownload

Description: alter cpld下载线制作方法集合，自己做就行，不用花40元去买了-alter cpld download cable production method of collection, make their own on the line, do not have to spend 40 yuan to buy a
Platform: | Size: 2455552 | Author: 高兵 | Hits:

[DSP program] Filtro

Description: Noise canceller with 40 bits data coded. Developed to implement over altera and xilix fpga
Platform: | Size: 9786368 | Author: viri | Hits:

[VHDL-FPGA-Verilog] synth_fft

Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT.
Platform: | Size: 56320 | Author: zzy | Hits:

[VHDL-FPGA-Verilog] jpeg_hardware.tar

Description: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co
Platform: | Size: 868352 | Author: | Hits:

[MPI] 40fpga

Description: 40个FPGA开发的简单实例，让初学者很好的入门。里面都有详细的程序设计思想说明。-You can use the verilog to realize a counter.
Platform: | Size: 46080 | Author: liu | Hits:

[VHDL-FPGA-Verilog] nano-logic

Description: 本手册适用于使用NANO-LOGIC CPLD 系列开发板的用户。 一款较高端FPGA 开发板既可以做项目开发也可以配上一个“通用的基础设备接口 板”作为新人培训入门使用 本产品的推出旨在于方便用户扩展基础设备和初学者学习使用。在FPGA 产品的设计 中，在初期调试时为了方便调试和显示程序工作状态，经常会用到大量的调试接口，比 如灯、按键、液晶显示等设备；这些设备既浪费有限的FPGA 资源又浪费宝贵的板卡体 积。本开发板提供了通常用户调试程序所需要的基础输入输出和上位机通讯接口，仅用 了6 个用户IO，扩展了相当于40 多个IO 的用户基础设备。这些用户基础设备可以并行 使用互不干扰。此开发板可以和本公司所用FPGA 产品配合使用，同时本开发板采用了 通用的2.54mm 连接器方便了用户与自己的FPGA 产品进行连接。-This manual applies to the use the NANO-LOGIC CPLD series development board user. A higher-end FPGA development board can do both project development can also be coupled with a common basis for device interface board as a new training started to use the product launch aimed at expansion of infrastructure and user-friendly for beginners to learn to use. To facilitate debugging and display program work state in the early debugging FPGA design often use a lot of debug interface devices such as lights, buttons, LCD these devices not only a waste of limited FPGA resources and waste valuable board volume. The development board provides the usual user debugger need basic input and output, and PC communication interface, only six user IO, and expansion of the user base is equivalent to more than 40 IO devices. User base device can be used in parallel without disturbing each other. This development board can be used by the Company with the use of FPGA products, at the same time, the developmen
Platform: | Size: 737280 | Author: 王培明 | Hits:

[Embeded Linux] asas

Description: 系统应用FPGA技术，通过VHDL编程，在CPLD上实现。电子琴的基本原理是产生各个音符对应的频率，将频率放大后驱动喇叭发出音响。该电子琴包括手动弹奏与自动演奏两种功能，其中手动弹奏时还可录音回放。文中叙述了电子琴的设计原理和分块实现的方法，详细介绍各模块的设计及模块之间的连接组合方法，还包括电子琴 -According to incomplete statistics, these companies represent about 40 of the domestic fiber laser marking market. It should be noted that this part of the market there is a significant reduction in price, a price close to the cost almost achieved. Although this is to walk in front of several vendors in a sufficient amount to promote the production scale, improve quality, and reduce costs, but to the entire industry brought "a good product but can not profit"
Platform: | Size: 6144 | Author: 黎明 | Hits:

[Software Engineering] xapp882

Description: This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s. The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew differences between the transmission paths of the data channels.-This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s. The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew differences between the transmission paths of the data channels.
Platform: | Size: 1026048 | Author: ylt_9811115 | Hits:

[VHDL-FPGA-Verilog] fp1-40-1_1

Description: fpga任意频率输出，精度《=2 ，串口控制分频系数，从50hz-51.2k精确分频，其中还包括小数点的处理。 通信部分：波特率处理模块、数据接受模块、数据校验及解码模块 分频部分：altpll锁相环模块，分频数计算模块、小数0.5检验模块、分频模块 -fpga any frequency output accuracy " = 2 , serial control division factor, from 50hz-51.2k precision divider, which also includes the decimal point processing. Communication part: baud processing module, data acceptance module, data validation and decoding module divider section: altpll phase-locked loop module, the division calculation module, decimal 0.5 test module, frequency module
Platform: | Size: 7120896 | Author: houjiajun | Hits:

[VHDL-FPGA-Verilog] 8-way-responder

Description: 基于FPGA实现8路抢答器功能 使用芯片为EP2C8Q208C8N,实现40秒内8路抢答功能，八路键盘输入，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。-8 based on FPGA Responder feature uses chips EP2C8Q208C8N, 40 seconds to achieve 8 Responder features eight keyboard input, using Verilog language programming, the present examples are engineering documents, simulation, waveform, tested can be used.
Platform: | Size: 1461248 | Author: 陈怡然 | Hits:

[VHDL-FPGA-Verilog] conf_fpga

Description: Configuration FPGA. Resources for EPM3128ATC100-10: macrocells: 47 pins: 40
Platform: | Size: 3773 | Author: vasil31 | Hits:

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