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[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269899 | Author: 王越 | Hits:

[Other resource] clock

Description: fpga clock 设计，资料较好，供大家参考，非商用目的哦
Platform: | Size: 2757 | Author: meng | Hits:

[SourceCode] Fpga clock modi

Description: 改程序是利用Fpga描述的 数字闹钟 带有铃声设置和闹钟设置
Platform: | Size: 2274027 | Author: ssongmu@sina.com | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的直接数字合成器设计

Description: 1、 利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、 利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、 输出波形要求： 在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz； 在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、 通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Platform: | Size: 21504 | Author: 竺玲玲 | Hits:

[Other Embeded program] 大型设计中FPGA的多时钟设计策略

Description: 大型设计中FPGA的多时钟设计策略,很详细的描述了在FPGA设计中时钟设计的方法-FPGA design large multi-clock design strategy, a very detailed description of the FPGA design clock design method
Platform: | Size: 101376 | Author: han | Hits:

[Books] fpga时钟设计

Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操 作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将 导致错误的行为，并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可 分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上 述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
Platform: | Size: 402432 | Author: 与言 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[Other] FPGATiming

Description: FPGA时钟分析，包括门控时钟与时钟偏仪分析，逻辑设计时钟分析，毛刺分析．-FPGA clock analysis, including clock gating and clock partial analysis, logic design clock analysis, Burr analysis.
Platform: | Size: 630784 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] clock

Description: fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh
Platform: | Size: 2048 | Author: max | Hits:

[Embeded-SCM Develop] FPGA_clock

Description: CPLD/FPGA设计中的时钟应用讲解 及其实例-CPLD/FPGA design applications on the clock and its examples
Platform: | Size: 920576 | Author: ZHUOHUI LI | Hits:

[assembly language] clock

Description: FPGA时钟设计程序代码，可调整时间，六位显示。
Platform: | Size: 2048 | Author: 张瑜婷 | Hits:

[Other] FPGA-Time

Description: FPGA的时钟详细讲解，可以让你更加熟悉的了解FPGA的时钟设计。-Explain in detail the FPGA clock, allowing you to become more familiar with understanding the design of FPGA clock.
Platform: | Size: 921600 | Author: skylinnan | Hits:

[VHDL-FPGA-Verilog] complex

Description: 时钟，信号灯verilog for FPGA -Clock signal verilog for FPGA
Platform: | Size: 3582976 | Author: zhaog gang | Hits:

[VHDL-FPGA-Verilog] create_200m

Description: 本代码用于产生FPGA内部的一个200Mhz的时钟，使得内部信号在此时钟下同步工作-The code used to generate a 200Mhz internal FPGA clock, the internal clock signal in this work under the synchronous
Platform: | Size: 2048 | Author: yang | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: 基于FPGA的多功能电子时钟的设计很经典的哦-FPGA-based multi-functional electronic clock designs are very classic Oh
Platform: | Size: 435200 | Author: xhb | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 大型设计中FPGA的多时钟设计策略,希望有需要的人喜欢-FPGA design of large-scale multi-clock design strategy, I hope there is a need of people like
Platform: | Size: 190464 | Author: 唐瑞 | Hits:

[VHDL-FPGA-Verilog] clock

Description: FPGA用lcd显示屏实现的24小时的计时器-FPGA with the lcd screen to achieve a 24-hour timer
Platform: | Size: 598016 | Author: wang wen tao | Hits:

[VHDL-FPGA-Verilog] FPGA-clock

Description: 基于VHDL的时钟设计（de2开发平台），内含源代码，各模块的时序仿真图，结构原理图，以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
Platform: | Size: 3565568 | Author: Bertrand | Hits:

[VHDL-FPGA-Verilog] FPGA-clock-for-chess

Description: 数字电路课程设计 FPAG的棋类时钟设计 -FPGA clock for chess
Platform: | Size: 406528 | Author: 张洁文 | Hits:

[VHDL-FPGA-Verilog] FPGA-clock

Description: FPGA的时钟资料，提供给大家参考。对学习FPGA有帮助-FPGA clock
Platform: | Size: 277504 | Author: zsfff | Hits:
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