Description: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful Platform: |
Size: 195584 |
Author:李华 |
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Description: 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计
-The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code description of the design process, operation circuit modeling, algorithm programming Platform: |
Size: 3852288 |
Author:betty |
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Description: 一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference Platform: |
Size: 356352 |
Author:menshuang |
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Description: 论文介绍了AES算法在FPGA上的实现功能，对AES算法过程进行了优化。-This paper introduces the AES algorithm in FPGA implementation function of the AES algorithm to optimize the process. Platform: |
Size: 645120 |
Author:朱丽丽 |
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Description: 基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process. Platform: |
Size: 13487104 |
Author:庄德坤 |
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Description: Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be
implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design
time while FPGA based implementation offers lower cost, quicker and more customizable solution. This paper
represents implementing AES in FPGA with minimum latency and speedy throughput where Verilog HDL is used
to simulate the operations. Platform: |
Size: 218112 |
Author:arif |
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Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by
using different architecture of mixcolumn. We then review this research investigates the AES algorithm in
FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera
Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of
transformations of both Encryptions and decryption are simulated using an iterative design approach in
order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation. Platform: |
Size: 191488 |
Author:Eric |
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Description: AES GCM 算法介绍，对AES算法实现有一定帮助。-This document aims to explore hardware implementation of GCM-AES mode of operation specifically targeting FPGA [1] (Field Programmable Gate Arrays). The aim of such an implementation is to benchmark GCM-AES on FPGA in terms of area, power and speed. Platform: |
Size: 254976 |
Author:宁进 |
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Description: This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware
implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications,
since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity
codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process.
The developed solution has been upgraded to an efficient BIST with a high fault coverage and a
low hardware overhead. Platform: |
Size: 940032 |
Author:ANU MOHAN |
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Description: The AES-128 implementation as depicted in Figure 3 has
been implemented on the FPGA. This required an initial
round key addition followed by ten rounds of S-Box. Platform: |
Size: 1024 |
Author:muthana |
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Description: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process. Platform: |
Size: 27648 |
Author:kutti
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