Search - fpga phy

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[Other resource] fpga_mac_vhdl DL : 0: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入
Update : 2008-10-13 Size : 309.31kb Publisher : 林大朋
[Other] fpga_mac_vhdl DL : 1: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入 -Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access
Update : 2025-02-17 Size : 309kb Publisher : 林大朋
[VHDL-FPGA-Verilog] sata_device_model DL : 0: sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
Update : 2025-02-17 Size : 16.61mb Publisher : 磊
[VHDL-FPGA-Verilog] mdio-md DL : 1: 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理-At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA completed by the MII management
Update : 2025-02-17 Size : 2kb Publisher : leon
[Embeded-SCM Develop] fpga DL : 0: fpga+sdram+PHY 芯片设计原理图-fpga+ sdram+ PHY chip design schematic
Update : 2025-02-17 Size : 63kb Publisher : liulei
[Communication] 80211b-simlink DL : 0: 802.11b simulink simulation source code for PHY layer. It can be used to generate bit-true test vector for RTL level design(FPGA).
Update : 2025-02-17 Size : 86kb Publisher : freedragon
[Program doc] wp_wimax DL : 0: WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and their key differences/applications. The PHY and MAC layers of a typical WiMAX base station are then described. The associated implementation challenges faced by WiMAX infrastructure developers, including performance/cost/flexibility trade-offs in the choice of silicon, are clearly outlined. The paper then describes how FPGA-based system implementation can address these challenges including the “accelerated time-to-market” requirement which is considered a key enabler for early success in this market. As an example design, the physical layer implementation of the 802.16d standard with Altera FPGAs and intellectual property (IP) is proposed.
Update : 2025-02-17 Size : 462kb Publisher : greg
[Internet-Network] TCPIPGuide_2-0_s9 DL : 0: WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and their key differences/applications. The PHY and MAC layers of a typical WiMAX base station are then described. The associated implementation challenges faced by WiMAX infrastructure developers, including performance/cost/flexibility trade-offs in the choice of silicon, are clearly outlined. The paper then describes how FPGA-based system implementation can address these challenges including the “accelerated time-to-market” requirement which is considered a key enabler for early success in this market. As an example design, the physical layer implementation of the 802.16d standard with Altera FPGAs and intellectual property (IP) is proposed.
Update : 2025-02-17 Size : 207kb Publisher : greg
[VHDL-FPGA-Verilog] m-mtip-10_100_1000_ethermac DL : 1: 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
Update : 2025-02-17 Size : 42kb Publisher : 天一生水
[VHDL-FPGA-Verilog] check_net_test DL : 0: 用来检查FPGA通过PHY发送数据时是否有掉帧的现象-FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of
Update : 2025-02-17 Size : 1kb Publisher : CHEN HAO
[VHDL-FPGA-Verilog] MII DL : 0: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Update : 2025-02-17 Size : 2kb Publisher : 雷伟林
[VHDL-FPGA-Verilog] DM9000A DL : 0: DM900 100M物理层PHY芯片FPGA连接，fpga实现数据链路层功能，完成网络数据的收发-DM900 100M physical layer PHY chip FPGA connections, fpga data link layer, the completion of the network to send and receive data
Update : 2025-02-17 Size : 18kb Publisher : zhangqiang
[VHDL-FPGA-Verilog] usb_phy_latest.tar DL : 0: USB phy latest for design USB by FPGA
Update : 2025-02-17 Size : 11kb Publisher : trung
[VHDL-FPGA-Verilog] USB_fpga DL : 0: FPGA与USB PHY芯片Cy7c68013A通信的程序，Verilog语言-FPGA and USB PHY chip Cy7c68013A communication procedures, Verilog language
Update : 2025-02-17 Size : 4.17mb Publisher : 路永轲
[VHDL-FPGA-Verilog] phyjingjian DL : 0: 通过fpga对phy芯片88e1111进行控制，可改变工作模式，传输速度等。-By fpga control of phy chip 88e1111 can change the working mode, the transmission speed.
Update : 2025-02-17 Size : 4.91mb Publisher : wanzhuan
[Software Engineering] DE2_NET DL : 0: DE2开发板例程源码，FPGA:EP2C35F256C6，代码基于quartus II 9.0以上的版本（随板光盘的为7.2的版本，在9.0以上的版本上编译通不过会报错）。该代码主要功能为FPGA对以太网通信，与PC机通信-In this demonstration, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. We use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY/MAC Controller.
Update : 2025-02-17 Size : 1.86mb Publisher : chenxin
[VHDL-FPGA-Verilog] help_lib DL : 1: 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)
Update : 2025-02-17 Size : 6.69mb Publisher : Nanke42
[Internet-Network] 100G以太网PCS子层研究及其在FPGA的实现 DL : 0: 主要描述了100G以太网物理层在XILINX FPGA上的实现方式(100G Ethertnet PHY, XILINX FPGA, Vivado)
Update : 2025-02-17 Size : 3.43mb Publisher : wanghuawen
[VHDL-FPGA-Verilog] DBSTAR_RGMII DL : 0: Verilog实现的RGMII和GMII接口转接，适合适配不同PHY芯片接口使用(Verilog implementation of RGMII and GMII interface transfer)
Update : 2025-02-17 Size : 4.9mb Publisher : zhzp
[Other] rgmii_image DL : 0: 通过RGMII协议驱动的PHY芯片完成千兆以太网收发，包括ARP响应(With RGMII driving PHY IC to finish the internet communication)
Update : 2025-02-17 Size : 4.15mb Publisher : MAOMAOSA

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