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[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] sdram4m16_L2_42

Description: 用FPGA实现SDRAM的操作，具体操作见内部说明文件-FPGA SDRAM with the operation of the specific see internal note
Platform: | Size: 263168 | Author: 陈雨 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3072 | Author: 林博 | Hits:

[MPI] SRAM_2

Description: FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序-FPGA SDRAM controller source FPGA SDRAM controller source
Platform: | Size: 553984 | Author: zlw | Hits:

[Other] ref-sdr-sdram-vhdl

Description: FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。-FPGA connected SDRAM source, VHDL language, the basic function fully. Application effective.
Platform: | Size: 732160 | Author: young | Hits:

[Program doc] FPGA

Description: SDRAM控制模块；图象采集系统说明性稳当；DSP图象采集系统。SDRAM作为存储器。-SDRAM control module image acquisition system illustrative trustworthy DSP image acquisition system. SDRAM as the memory.
Platform: | Size: 179200 | Author: yan | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 基于FPGA的SDRAM控制器的设计和实现,还比较好勒.-FPGA-based SDRAM controller design and realization, but also better le.
Platform: | Size: 69632 | Author: rubyshirial | Hits:

[VHDL-FPGA-Verilog] (fpga)sdram

Description: verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件-Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
Platform: | Size: 19935232 | Author: ch | Hits:

[VHDL-FPGA-Verilog] AlteraSDR-SDRAM

Description: Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Platform: | Size: 811008 | Author: machenghai | Hits:

[Embeded-SCM Develop] fpga

Description: fpga+sdram+PHY 芯片设计原理图-fpga+ sdram+ PHY chip design schematic
Platform: | Size: 64512 | Author: liulei | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing
Platform: | Size: 2171904 | Author: jyb | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog 128位 突发4. sdr fpga控制器-verilog 128 bit unexpected 4. sdr fpga controller
Platform: | Size: 119808 | Author: pudnrtest | Hits:

[VHDL-FPGA-Verilog] fpga-dm9000a

Description: 一个项目工程，硬件包含XINLINX FPGA，配置FLASH，串口，SDRAM,与以太网芯片DM9000A，实现数据采集，以太网传输，电路验证完全正确，请放心使用，SPARTAN 3E 的BGA引脚320个，不容易布板，可以参考使用的。要FPGA实现网络通信也可以参考电路，B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SDRAM, and Ethernet chips DM9000A, data acquisition, Ethernet transmission, circuit verification is completely correct, please rest assured that the use of, SPARTAN 3E' s 320-pin BGA it is not easy layout, you can reference to use. To achieve network communication FPGA also can refer to the circuit, because the product upgrades so publicly.
Platform: | Size: 915456 | Author: rong | Hits:

[Other] SDR-SDRAM-ctl1

Description: SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
Platform: | Size: 718848 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface
Platform: | Size: 388096 | Author: gdr | Hits:

[VHDL-FPGA-Verilog] sdram-source

Description: SDR SDRAM 控制器的源代码 altera公司的-source code from altera
Platform: | Size: 717824 | Author: wela | Hits:

[VHDL-FPGA-Verilog] sdram

Description: how to use sdram ip ， just for fpga
Platform: | Size: 458752 | Author: baoyu | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: FPGA SDRAM控制器Verilog源码，通过测试-FPGA SDRAM VERILOG
Platform: | Size: 5120 | Author: 大海 | Hits:

[VHDL-FPGA-Verilog] SDRAM-controller-design-FPGA-based

Description: 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
Platform: | Size: 3163136 | Author: connie | Hits:
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