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Description: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
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Size: 2572288 |
Author: 李晨 |
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Size: 14336 |
Author: 顾向南 |
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Description: 用上位机UART控制一个十字路口的交通灯的.v文件。包括testbench在内，可用FPGA cycloneII DE270跑仿真。-traffic lights at a crossroads. V file controlled by PC UART. Including testbench , available FPGA cycloneII DE270 run the simulation.
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Size: 3954688 |
Author: 张宁 |
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Description: FPGA的串口通信 v 文件，直接编译就可以串口通信了，波特率9600(FPGA serial communication, V file)
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Size: 1024 |
Author: shishi21
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