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[Other resource] an_dcfifo_top_restored DL : 2: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输，值得学习。
Update : 2008-10-13 Size : 906.86kb Publisher : alison
[VHDL-FPGA-Verilog] FPGA控制VGA显示（Verilog） DL : 2: 用FPGA开发板控制VGA显示，以800*600的分辨率，首先在屏幕的正中央依次出现“新”“年”“快”“乐”四个汉字，并分别移动到屏幕的四个角落，接着在屏幕中部从左至右依次出现“Happy New Year”英文字样，然后出现三个由小到大再消失的圆形图标模拟烟花，最后在黑屏中闪烁金星。字体均采用不同颜色，增添喜庆气氛。本代码是练习VGA控制，ROM调用，时序控制及状态机运用的一个综合实例！
Update : 2010-10-28 Size : 11.34kb Publisher : hangman_102@126.com
[VHDL-FPGA-Verilog] 用FPGA实现DDS信号发生及用MODELSIM仿真 DL : 1: 该工程是用verilog编写，FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
Update : 2011-03-21 Size : 2.41mb Publisher : zhengguo22
[VHDL-FPGA-Verilog] VHDL语言100例详解 DL : 0: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Update : 2025-02-17 Size : 6.33mb Publisher : 穆群生
[VHDL-FPGA-Verilog] sine DL : 0: Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Update : 2025-02-17 Size : 4.57mb Publisher : 陈剑
[VHDL-FPGA-Verilog] alteraexample DL : 0: CPLD/FPGA常用模块与综合系统设计实例光盘程序-CPLD/FPGA module with commonly used integrated system design example CD-ROM program
Update : 2025-02-17 Size : 16.65mb Publisher : 徐
[VHDL-FPGA-Verilog] an_dcfifo_top_restored DL : 0: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Update : 2025-02-17 Size : 907kb Publisher : alison
[VHDL-FPGA-Verilog] rom DL : 0: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Update : 2025-02-17 Size : 636kb Publisher : jimmy
[VHDL-FPGA-Verilog] verilog DL : 0: 《数字信号处理的FPGA实现》（第二版）光盘verilog代码-" The FPGA digital signal processing to achieve" (second edition) CD-ROM code verilog
Update : 2025-02-17 Size : 323kb Publisher : 王昊
[VHDL-FPGA-Verilog] rom DL : 0: 基于Verilog语言编写的各种只读存储器rom和随机存储器ram-Verilog language based on a variety of read-only memory rom and random access memory ram
Update : 2025-02-17 Size : 688kb Publisher : 李辽原
[Other] VerilogHDL-FPGA DL : 0: Verilog HDL程序设计实例详解光盘 FPGA-Verilog HDL programming example explanation of CD-ROM
Update : 2025-02-17 Size : 19.02mb Publisher : 蔡新林
[3G develop] DDFS_verilog DL : 0: 直接数字频率综合器，采用ROM压缩法，经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation
Update : 2025-02-17 Size : 5kb Publisher : jessie
[VHDL-FPGA-Verilog] VGA_char_ROM_success DL : 0: Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the character data storage and VGA display, pin assignment for the EP2C8Q208 21EDA development board, for a detailed explanation you can see 《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》in the book《深入浅出玩转FPGA》.
Update : 2025-02-17 Size : 767kb Publisher : LM
[VHDL-FPGA-Verilog] romPlcd1602 DL : 0: 用verilog hdl实现从fpga内部rom中读取数据在lcd1602上显示-The data in the fpga rom is read out and shown in lcd1602 by verilog hdl
Update : 2025-02-17 Size : 3kb Publisher : sxy
[VHDL-FPGA-Verilog] ram DL : 0: 基于FPGA的rom程序（verilog）-rom procedure
Update : 2025-02-17 Size : 2kb Publisher : 杨涛
[VHDL-FPGA-Verilog] rom-test DL : 0: 简单的FPGA中ROM使用仿真程序，使用的verilog语言-Simple FPGA ROM emulator, using the verilog language
Update : 2025-02-17 Size : 9.27mb Publisher : blue
[VHDL-FPGA-Verilog] music_player DL : 1: 用Verilog语言在FPGA上实现了音乐播放这一功能。预先将音乐《北京欢迎你》转换保存到FPGA的ROM中，由设计的音乐播放器按时序读出数据，予以播放。-Using Verilog language in FPGA realize the function of playing music.The music of "welcome to Beijing" was transformed and saved in FPGA ROM, the data was read by music player in the time sequence and played .
Update : 2025-02-17 Size : 713kb Publisher : 姜伟
[VHDL-FPGA-Verilog] verilog-midi-reader-master DL : 0: MIDI file parser that converts song and lyric data to Verilog ROM format for use on an FPGA
Update : 2025-02-17 Size : 22kb Publisher : 小海豚
[VHDL-FPGA-Verilog] rom_test DL : 0: rom读写实验，实现FPGA内部rom数据存取(rom read and write,this is a good document for study FPGA verilog)
Update : 2025-02-17 Size : 4.05mb Publisher : konan007
[matlab] 数字滤波器的MATLAB与FPGA实现例程代码567 DL : 0: 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第5、6、7章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter well with e-book use, complete code, good simulation, the chapter 5 6 7))
Update : 2025-02-17 Size : 27.2mb Publisher : wanmei10

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