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[Other resource] vhdl-dds

Description: fpga 控制dds 程序。希望对各位有用
Platform: | Size: 87754 | Author: martin | Hits:

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Platform: | Size: 5120 | Author: 胡玉贵 | Hits:

[Communication-Mobile] DDFS_PLL_10DA_with51

Description: FPGA下的DDS程序的编写,VHDL语言,-FPGA under DDS preparation procedures, VHDL language,
Platform: | Size: 627712 | Author: huang | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS正弦信号发生器 频率和相位连续可调。频率最大2M
Platform: | Size: 3072 | Author: dsf | Hits:

[VHDL-FPGA-Verilog] dds

Description: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Platform: | Size: 468992 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] vhdl-dds

Description: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Platform: | Size: 88064 | Author: martin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
Platform: | Size: 2098176 | Author: wade | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

[VHDL-FPGA-Verilog] dds

Description: fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
Platform: | Size: 571392 | Author: wangjian | Hits:

[VHDL-FPGA-Verilog] dds

Description: 如何利用FPGA产生DDS调频信号 很具体的-How to make use of DDS generated FM signal FPGA specific
Platform: | Size: 756736 | Author: 梁梁 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] prog_dds

Description: FPGA VHDL DDS程序，采用FPGA实现1hz到100khz可调的dds程序，频率调节步长是变化的。-FPGA VHDL DDS program, using FPGA to achieve 1hz to 100khz adjustable dds procedures, the frequency adjustment step size is changing.
Platform: | Size: 1240064 | Author: 张鹏 | Hits:

[VHDL-FPGA-Verilog] DDS-FPGA

Description: 基于FPGA的DDS资料！个人搜集的 可直接编译-FPGA-based DDS information!
Platform: | Size: 6350848 | Author: eva | Hits:

[Software Engineering] DDS-FM-FPGA

Description: DDS介绍,FM信号发生器的设计!基于DDS技术的FM信号发生器的设计及其FPGA实现-DDS introduced, FM Signal Generator! FM signal based on DDS technology and FPGA Implementation Generator
Platform: | Size: 356352 | Author: 雨夜里 | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 这是基于FPGA的直接数字频率合成器的程序，是VHDL语言-This is based on FPGA for direct digital frequency synthesizer program that is VHDL language
Platform: | Size: 1253376 | Author: 笙箫 | Hits:
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