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[assembly languagecpld

Description: 一个好用的整数分频电路 保证你喜欢 能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
Platform: | Size: 915 | Author: 王多奎 | Hits:

[Embeded-SCM Developmax1

Description: cpld数据采集测频-cpld Frequency Measurement Data Collection
Platform: | Size: 5120 | Author: 和任 | Hits:

[Other Embeded program低频数字式相位测量仪

Description: 低频数字式相位测量仪; 此系统由相位测量仪、数字式移相信号发生器和移相网络三部分组成。为使系统更加稳定,使系统整体精度得以保障,本电路两块T89C52为核心控制器件分别控制相位测量、数字式移相信号发生,在数字式移相信号发生部分采用了锁相技术、CPLD等技术, 使输出波形精度大大提高,并可对频率自动校验,提高频率稳定性。-low-frequency digital phase-measuring instrument; This system consists of phase-measuring instrument, digital phase shifting generator and phase three network components. To make the system more stable, the overall accuracy of the system can be protected, the two T89C52 circuit control devices at the core respectively phase measurement control, digital believe the shift occurred, the digital shift occurred some believe that the use of lock-in technologies, such as CPLD technology, the output waveform accuracy greatly improved, and can automatic calibration frequency, frequency stability.
Platform: | Size: 433152 | Author: 逸飞 | Hits:

[ARM-PowerPC-ColdFire-MIPSjtag_cpld_vhdl

Description: JTAG CPLD实现源代码,比用简单并口调试器快5倍以上。 以前总觉得简单的并口jtag板速度太慢,特别是调试bootloader的时候,简直难以忍受。最近没什么事情,于是补习了几天vhdl,用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15,晶振20兆,tck频率5兆。用sjf2410作测试,以前写50k的文件用时5分钟,现在则是50秒左右。tck的频率还可以加倍,但是不太稳定,而且速度的瓶颈已经不在tck这里,而在通讯上面了。 -JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: | Size: 2048 | Author: 李伟 | Hits:

[VHDL-FPGA-Verilogbeipin

Description: 用verilog写的cpld的各种分频程序,希望大家指正,谢谢!-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
Platform: | Size: 1024 | Author: 沈柱 | Hits:

[MiddleWarebeipin_quartII

Description: 在FPGA或CPLD上实现的一中非常实用的倍频电路,只要输入频率高,精度就很高-the CPLD or FPGA to achieve a very practical frequency circuit, as long as the input frequency, on the high precision
Platform: | Size: 75776 | Author: 王石子 | Hits:

[Program doctriphace

Description: 基于可编程逻辑器件CPLD和直接数字频率合成技术(DDS)的三相多波形函数发生器-based CPLD and direct digital frequency synthesis (DDS) over the three-phase waveforms letter Number Generator
Platform: | Size: 92160 | Author: liujl | Hits:

[Software Engineeringcpldtodds

Description: dds信号发生器程序设计,框图,基于CPLD控制的DDS数字频率合成器设计-dds signal generator program design, block diagram, the CPLD based on DDS Digital Frequency Synthesizer Design
Platform: | Size: 89088 | Author: yaoming | Hits:

[VHDL-FPGA-Verilogchip1

Description: CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
Platform: | Size: 30720 | Author: sss | Hits:

[SCMCPLDMCUFREQUENCY

Description: 用单片机AT89s52和epm7128设计的频率计-MCU AT89s52 epm7128 design and the frequency meter
Platform: | Size: 2048 | Author: frankcai | Hits:

[assembly languagecpld

Description: 一个好用的整数分频电路 保证你喜欢 能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
Platform: | Size: 1024 | Author: 王多奎 | Hits:

[Embeded-SCM DevelopCPLD234

Description: 文档中给出了使用VHDL编写的频率的精确测量方法的代码,同时还有cPLD与e2rom等的接口代码-Document given the frequency of the use of VHDL to prepare precise measurement method of the code, along with e2rom CPLD interface code, etc.
Platform: | Size: 223232 | Author: qibinchuan | Hits:

[SCMcpld

Description: 用于频率测量,使用CPLD,单片机可进行测试。-For frequency measurement, the use of CPLD, single-chip can be tested.
Platform: | Size: 320512 | Author: | Hits:

[Software EngineeringFPGA

Description: 系统应用FPGA技术,通过VHDL编程,在CPLD上实现。电子琴的基本原理是产生各个音符对应的频率,将频率放大后驱动喇叭发出音响。该电子琴包括手动弹奏与自动演奏两种功能,其中手动弹奏时还可录音回放。文中叙述了电子琴的设计原理和分块实现的方法,详细介绍各模块的设计及模块之间的连接组合方法,还包括电子琴的使用说明。-System FPGA technology, the adoption of VHDL programming, to achieve in the CPLD. The basic principles of flower is the corresponding frequency of each note will be the frequency of enlarged issued after the driver speaker audio. Playing the organ, including manual and automatic playing two functions, which also play recordable playback manually. The paper describes the design of flower and block the realization of the principle of the method, details of the module design and module combination of the connection between the methods also include the use of electric piano note.
Platform: | Size: 49152 | Author: 严术骞 | Hits:

[DocumentsCPLD

Description: 针对超声波应用系统易受噪声干扰以及超声波信号的空间衰减现象影响, 从而要求 超声波传感器工作在其最佳特性的特点, 论证了驱动脉冲信号的控制精度对传感器工作特 性的影响, 给出了传感器驱动信号脉冲宽度与传感器频率之间的最佳关系式, 提出了采用复 杂可编程逻辑器件(CPLD) 产生传感器驱动控制信号的方法, 将该方法应用于一超声波流 量计测量系统中, 得到了比传统型单片机控制电路更好的控制精度和控制效果。-For ultrasonic applications vulnerable to noise interference and attenuation of ultrasonic signals in the effects of space and thus require ultrasonic sensors work best features in its characteristics, demonstrated that the drive pulse signal of the control accuracy of the sensor characteristics of the work, given the sensor-driven signal pulse width and frequency sensors of the best relationship between the proposed use of complex programmable logic device (CPLD) have a sensor-driven control signal approach, the method is applied to one ultrasonic flowmeter measurement system has been more than traditional single-chip control circuit better control precision and control.
Platform: | Size: 223232 | Author: 李明 | Hits:

[SCMS51+CPLD

Description: 基于等精度测量原理的频率计,AT89S52和CPLD,有详细注释。测量准确。-Such as precision measurement principle based on the frequency meter, AT89S52 and CPLD, has detailed notes. Measurement accuracy.
Platform: | Size: 284672 | Author: MAZEMIN | Hits:

[Software EngineeringCPLD

Description: 在电子技术中,频率是最基本的参数之一,又与许多电参量的测量方案、测量结果都有十分密切的关系,因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速,以及便于实现测量过程自动化等优点,是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计,并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门,通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率,最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求,而且具有了单片机的稳定性和成熟性,且控制能力强,是一种低成本,高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Platform: | Size: 192512 | Author: 张林锋 | Hits:

[Other Embeded programcpld

Description: 测量范围要求 1Hz-10MHz(输入信号幅度为0.5V-5V)。 基本性能要求 f为10MHz时,频率绝对误差不大于1000Hz; (高频精度) f小于1000Hz时,频率绝对误差不大于1Hz。 (低频精度) 提高性能要求 高频精度提高: f为10MHz时,频率绝对误差不大于100Hz。 低频精度提高:f小于1000Hz时,频率绝对误差不大于0.5Hz。 -Requirements of measuring range 1Hz-10MHz (input signal range of 0.5V-5V). F the basic performance requirements for the 10MHz, the frequency of absolute error not more than 1000Hz (high-frequency accuracy) f less than 1000Hz, the frequency of absolute error no greater than 1Hz. (Low-frequency accuracy) to improve the accuracy of performance requirements to improve high-frequency: f to 10MHz, the frequency of absolute error not more than 100Hz. Low-frequency accuracy: f is less than 1000Hz, the frequency of absolute error no greater than 0.5Hz.
Platform: | Size: 161792 | Author: 梁晓豪 | Hits:

[OtherCPLD

Description: The output frequency requirements for the three waveforms are: the frequency range is adjustable between 20Hz-20kHz; the phase difference between the three waveforms is 120 degrees. A. of sine wave signal: step 10Hz; frequency stability: better than 1/10000; nonlinear distortion coefficient is less than 3%. B. of the square wave signal is frequency: the rise and fall time of <1 s; The requirements of C. for triangular wave signals are that the signal frequency range is adjustable between 20Hz-20kHz. D. for the above three frequencies are required: the frequency can be preset; when the load is 600, the output signal amplitude is greater than 3V; the output signal amplitude can be adjusted in the range of 100mv~3V, the step length is 100mV.
Platform: | Size: 360448 | Author: 东京的樱花飘过巴黎 | Hits:

[Windows DevelopCPLD-FREQUENCY CONTROL

Description: 通过手动和自动方式对输出频率进行设置,通过锁相环输出。(The output frequency is set by manual and automatic mode, and output by the phase locked loop.)
Platform: | Size: 1494016 | Author: 小锐锐 | Hits:
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