Search - frequency divider

[VHDL-FPGA-Verilog] Verilog_FPGA_fp

Description: 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
Platform: | Size: 124928 | Author: xiong | Hits:

[File Format] VHDLEXAMPLEppt

Description: 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
Platform: | Size: 527360 | Author: 刘一 | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of
Platform: | Size: 35840 | Author: digua | Hits:

[Windows Develop] clock-divider

Description: 这是一个关于时钟分频率器的程序，它可以实现频率的扩大。-This is a device on the clock frequency of the procedure, it can realize the expansion of the frequency.
Platform: | Size: 1024 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] te187

Description: 基于高速串行BCD 码除法的数字频率计的设计-Based on high-speed serial BCD code of the digital frequency divider Design
Platform: | Size: 208896 | Author: 张贺寅 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed description of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL examples)
Platform: | Size: 23552 | Author: xiang | Hits:

[source in ebook] frequency

Description: frequency divider circuit divides the input frequency (clk) by various factors
Platform: | Size: 1024 | Author: sad | Hits:

[VHDL-FPGA-Verilog] f_divider

Description: 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
Platform: | Size: 455680 | Author: abu_faisul | Hits:

[Other] FF_Divider_ISCAS04

Description: A Novel Ultra High Speed Flip Flop Base Frequency Divider
Platform: | Size: 154624 | Author: bamadude | Hits:

[Other] Freq_Divider

Description: frequency divider using verilog
Platform: | Size: 1024 | Author: hazwaj | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[VHDL-FPGA-Verilog] Fredevider_n

Description: 任意N偶数倍频率分频器VHDL语言，编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
Platform: | Size: 24576 | Author: 黑雾 | Hits:

[VHDL-FPGA-Verilog] diwu

Description: 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
Platform: | Size: 10240 | Author: 小杰 | Hits:

[VHDL-FPGA-Verilog] frequency-divider

Description: anything frequency divider-frequency divider
Platform: | Size: 1024 | Author: wudongdong | Hits:

[MiddleWare] Simplified-2-frequency-divider

Description: 用verilog语言编写的两个2分频小程序，通过了验证。-Two small written in Verilog language frequency divider applet, passes validation.
Platform: | Size: 3072 | Author: zhangjinbao | Hits:

[Other Embeded program] Frequency-divider

Description: 本例程为简易分频器。实验前，请用排线（杜邦线）将TX-1C学习板的P1^0管脚与P3^2(INT0)管脚相连。因为P1^0用来模拟外界波形输入，它提供周期为100ms的方波，与T1管脚相连后，T1可对其进行周期计数。程序中的变量pp决定着分频系数，其值乘以2即为分频系数。改变其值可以得到相应的分频输出波形（方波）。P1^1为输出管脚，将其连接示波器可以看到分频后的波形。-This routine for simple frequency divider. Before experiment, please use platoon line (dupont line) will TX- 1 c ^ 0 learning plate P1 of the pin and P3 ^ 2 (INT0) pin connected. Because P1 ^ 0 used to simulate the outside world wave input, it provides cycle for 100 ms square wave, and T1 pin connected, T1 can carry on the cycle count. The procedure in the variable pp determines the scale coefficient, the value multiplied by 2 is the crossover factor. To change its value can get corresponding crossover output waveform (square). P1 ^ 1 as output pin, its connection oscillograph can see points after the frequency of the wave.
Platform: | Size: 22528 | Author: zhanghuasheng | Hits:

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[VHDL-FPGA-Verilog] Verilog_FPGA_fp

[File Format] VHDLEXAMPLEppt

[VHDL-FPGA-Verilog] clk_div

[Windows Develop] clock-divider

[VHDL-FPGA-Verilog] te187

[VHDL-FPGA-Verilog] Frequency_divider

[VHDL-FPGA-Verilog] clock_divider

[source in ebook] frequency

[VHDL-FPGA-Verilog] f_divider

[Other] FF_Divider_ISCAS04

[Other] Freq_Divider

[source in ebook] sanfenpin

[VHDL-FPGA-Verilog] Fredevider_n

[VHDL-FPGA-Verilog] diwu

[VHDL-FPGA-Verilog] frequency-divider

[MiddleWare] Simplified-2-frequency-divider

[Other Embeded program] Frequency-divider

[VHDL-FPGA-Verilog] frequency-divider

[VHDL-FPGA-Verilog] Frequency-divider

[VHDL-FPGA-Verilog] frequency divider and testbench

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