Description: EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time - with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized) Platform: |
Size: 3131 |
Author:李培 |
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Description: EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized) Platform: |
Size: 3072 |
Author:李培 |
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Description: vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of Platform: |
Size: 35840 |
Author:digua |
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Description: DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)
为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.-DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low. Platform: |
Size: 1024 |
Author: |
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Description: 本例展示了如何利用外设TIM2来产生四路频率不同的信号。
TIM2时钟设置为36MHz，预分频设置为2，使用输出比较-翻转模式（Output Compare Toggle Mode）。
TIM2计数器时钟可表达为：TIM2 counter clock = TIMxCLK / (Prescaler +1) = 12 MHz
设置TIM2_CCR1寄存器值为32768，则CC1更新频率为TIM2计数器时钟频率除以CCR1寄存器值，为366.2 Hz。因此，TIM2通道1可产生一个频率为183.1 Hz的周期信号。
同理，根据寄存器TIM2_CCR2 、TIM2_CCR3和 TIM2_CCR4的值，TIM2通道2可产生一个频率为366.3 Hz的周期信号；TIM2通道3可产生一个频率为732.4 Hz的周期信号；TIM2通道4可产生一个频率为1464.8 Hz的周期信号。
可以通过示波器观察各路输出-This example demonstrates how to use peripherals TIM2 to generate four different signal frequencies. TIM2 clock set to 36MHz, pre-divider is set to 2, the use of output compare- flip model (Output Compare Toggle Mode). TIM2 counter clock can be expressed as: TIM2 counter clock = TIMxCLK/(Prescaler+ 1) = 12 MHz set TIM2_CCR1 register value is 32768, then cC1 update frequency for TIM2 counter clock frequency divided by the value of CCR1 register for 366.2 Hz. Therefore, TIM2 channel 1 can generate a frequency of 183.1 Hz for the periodic signal. Similarly, under the register TIM2_CCR2, TIM2_CCR3 and TIM2_CCR4 value, TIM2 channel 2 can have a frequency of 366.3 Hz cycle signal TIM2 channel 3 can have a frequency of 732.4 Hz cycle signal TIM2 Channel 4 can produce a frequency of 1464.8 Hz cycle signal. Can be observed through the oscilloscope various output Platform: |
Size: 209920 |
Author:chen |
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Description: DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.
-DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal_in and signal_out the code rate of 2 times) to clk/8/N. modulus K K value addition and subtraction counter DPLL decision to establish the accuracy and synchronization time, K is larger, the simultaneous establishment of a long time, synchronization accuracy. contrary is short and low. Platform: |
Size: 1024 |
Author:鬼舞十七 |
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Description: 由VHDL撰写的强大多功能除频器，只需由上方参数载入除频数N及N的宽度(2的次方)即可使用。
可以除以任意整数，包含奇数。-Written by the powerful multi-functional VHDL divider, just above the parameters included in addition to the frequency width of N, N-(2 power) can be used. Can be divided by any integer, including odd. Platform: |
Size: 288768 |
Author:Risger |
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Description: 只用单片机实现20Mhz不现实,但可以把频率信号分频,比附超过100K之后就给他2分频,随着频率增加,分频值增加,分频电路需另加硬件,然后分档,分档后的频率测量程序可以用下面的方法测量.-
20Mhz MCU only unrealistic, but the frequency of the signal frequency, after the analogy gave him more than 100K divided by 2, as the frequency increases, the value of increased frequency, frequency divider circuit are subject to hardware, and then sub-file, sub-file after the frequency measurement process can be measured using the following method.
Platform: |
Size: 4096 |
Author:suzhou |
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Description: 将信号波形数据存放在EEROM中，通过74LS393分频产生不同频率的刷新信号，输出存储器的数据，由DA输出，产生不同频率的信号。.
-The signal waveform data stored in EEROM, through the 74LS393 frequency divider to produce different frequency refresh signal, output of memory data, output by the DA, generate signals of different frequency. Platform: |
Size: 84992 |
Author:刘清 |
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Description: 硬件电路主要分为信号转换电路、分频电路、数据选择电路、单片机系统和显示电路五部分。
电平转换电路：
电平转换电路的必要性：因为在单片机计数中只能对脉冲波进行计数，而实际中需要测量的频率的信号是多种多样的，有脉冲波，还有可能有正弦波、三角波等，所以需要一个电路把待测信号可以进行计数的脉冲波。
通过电平转化电路将正弦输入信号fx整形成同频率方波fo,要将正弦信号转换成方波信号可以用过零比较电路实现。正弦信号通过LM833N与零电平比较，电压大于零的时候输出LM833N的正电源+5V，电压小于零的时候输出负电源0V。
-Hardware circuit can be divided into signal conversion circuit, frequency divider circuit, the data selection circuit, single-chip systems, and display circuit of five parts.
Level-shifting circuit:
The need for level-shifting circuit: as in the MCU can only count on the pulse count, but the actual need to measure the frequency of the signal is varied, a pulse wave, there may be sine, triangle, etc. so they need a circuit to test the signal pulse can be counted.
By the level conversion circuit to form a sinusoidal input signal with frequency fx entire square wave fo, convert square wave to sine wave signal can be used to achieve zero comparator circuit. Sinusoidal signal with the zero level by LM833N comparison, the voltage output of LM833N greater than zero when the positive power supply 5V, output voltage is less than zero, the negative power supply 0V. Platform: |
Size: 412672 |
Author:华一 |
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Description: 分频器有2分频16分频8分频也可用于其他分频-Divider have divided by 16 divided by 8 divide can also be used for other frequency division Platform: |
Size: 1024 |
Author:夏小顺 |
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Description: 基于xilinx spartan 3e 开发板的ATMEL 25c 系类EEPROM 接口程序。可以将EEPROM值读出并显示于LCD上。读取频率由DCM和内部分频器控制。读出结果可以自动和设定值（55AA 或AA55等）进行比对，并也在LCD上显示verify的结果。 通过switch可以选择连续读出整个存储空间，或是通过button按字节读取。-Based on the xilinx spartan 3e development boards of ATMEL 25c Department of class EEPROM interface program. The EEPROM values can be read out and displayed on the LCD. Read frequency is controlled by the DCM and the internal divider. Read out the results can be automatically set value (55AA or AA55) to compare and verify results and also displayed on the LCD. Switch can select the continuous read out the entire storage space, or through the button to read bytes. Platform: |
Size: 1647616 |
Author:李华 |
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Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。
下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。
-In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the clock signal in the hardware circuit design is very important. Here we introduce the VHDL description of the divider in the source code of the clock signal CLK divided by 2, 4 divider, divide by 8, divided by 16. Platform: |
Size: 86016 |
Author:zhanghua |
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Description: 本例程为简易分频器。 实验前，请用排线（杜邦线）将TX-1C学习板的P1^0管脚与P3^2(INT0)管脚相连。因为P1^0用来模拟外界波形输入，它提供周期为100ms的方波，与T1管脚相连后，T1可对其进行周期计数。 程序中的变量pp决定着分频系数，其值乘以2即为分频系数。 改变其值可以得到相应的分频输出波形（方波）。P1^1为输出管脚，将其连接示波器可以看到分频后的波形。-This routine for simple frequency divider. Before experiment, please use platoon line (dupont line) will TX- 1 c ^ 0 learning plate P1 of the pin and P3 ^ 2 (INT0) pin connected. Because P1 ^ 0 used to simulate the outside world wave input, it provides cycle for 100 ms square wave, and T1 pin connected, T1 can carry on the cycle count. The procedure in the variable pp determines the scale coefficient, the value multiplied by 2 is the crossover factor. To change its value can get corresponding crossover output waveform (square). P1 ^ 1 as output pin, its connection oscillograph can see points after the frequency of the wave.
Platform: |
Size: 22528 |
Author:zhanghuasheng |
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Description: 时钟分频器原理与实现，计数跳变的频率和加减模式可实时变化，通过Nano实验板上的LCD显示器显示。计数频率、加减选择和初始化操作通过板上的拨动开关和Reset按钮实现。-Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nano experiments. Counting frequency, subtraction selection and initialization by a toggle switch panel and Reset buttons to achieve. Platform: |
Size: 818176 |
Author:范鹏 |
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Description: The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group.-The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group. Platform: |
Size: 4096 |
Author:ehsan |
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Description: EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with
complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter
system or DC-AC single stage low power frequency transformer system for boosting. EG8010 can
achieve 50/60Hz pure sine wave with high accuracy, low harmonic and distortion by external
12MHz crystal oscillator. EG8010 is a CMOS IC that integrates SPWM sinusoid generator, dead
time control circuit, range divider，soft start circuit, circuit protection, RS232 serial communication,
12832 serial LCD unit, and etc. Platform: |
Size: 239616 |
Author:jofre |
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Description: 这是内部有10位ADC的一个简单应用，这个电路最多测量30 V DC，可以应用在台式电源或各种系统中的面板仪表。
PIC16F676的内部adc与一个电阻网络分压器用于测量输入电压，用数码管来显示电压值，频率在50HZ左右
在原理图中的47K看到和10K电位连接分压器配置。在默认情况PIC微控制器ADC参考电压设置到VCC（+ 5V在这种情况下），分出最大射程30伏到5伏这样的分压器。(This is a simple application with 10 bit ADC inside. This circuit measures at most 30 V DC, and can be used in desktop power supply or panel meters in various systems.
PIC16F676 internal ADC and a resistor network divider used to measure the input voltage, digital tube to display voltage values, the frequency is about 50HZ
In the schematic, the 47K is seen and the 10K potential is connected to the voltage divider configuration. By default, the PIC microcontroller ADC reference voltage is set to VCC (+ 5V in this case), dividing the maximum range from 30 volts to 5 volts for such a voltage divider.) Platform: |
Size: 6144 |
Author:华仔华仔
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