Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed. Platform: |
Size: 179200 |
Author:李中伟 |
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Description:
1.利用FLEX10KE系列（EPM10K100EQC240-1X）的CLOCKBOOST
（symbol:CLKLOCK）,设计一个2倍频器，再将该倍频器2分频后输出。
对其进行时序仿真。
2.设计一个数据宽度8bit，深度是16的
同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。
要求FIFO的读写时钟频率为20MHz，
将1－16连续写入FIFO，写满后再将其读出来（读空为止）。
仿真上述逻辑的时序，将仿真波形打印出来（与第1题放在同一个PROJECT中）。
3.设计一个数据宽度8bit，深度是16的异步FIFO（读写时钟不相同），
当读写时钟的频率分别为wrclk＝40MHz、rdclk＝20MHz时，仿真其逻辑波形。
-1. FLEX10KE series using (EPM10K100EQC240-1X) of CLOCKBOOST (symbol: CLKLOCK), the design of a 2 frequency multiplier, and then the multiplier 2 hours after the output frequency. Its timing simulation. 2. The design of a data width of 8bit, depth of 16 synchronous FIFO (read and write with the same clock), with EMPTY, FULL output signs. FIFO read and write requests of the clock frequency of 20MHz, the 1-16 consecutive write FIFO, written after the read (read until empty). Simulation of the above-mentioned logical timing, simulation waveforms will print out (with the No. 1 title on the same PROJECT in). 3. To design a data width of 8bit, the depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation waveform of its logic. Platform: |
Size: 53248 |
Author:李侠 |
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Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK. Platform: |
Size: 208896 |
Author:何蓓 |
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Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift. Platform: |
Size: 1024 |
Author:杨化冰 |
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Description: 单片机设计了一种单片锁相倍频电
路，利用片内定时器和数字算法实现了对输入信号的同步
锁相和倍频，并输出倍频信号-: A single- chip digital phase- locking frequency- multi-
plier circuit is designed based on the AT89c2051.The circuit
can track the input signal in- phase and output the frequency-
multiplier signal. It is verified by the experiment results that the
design is correct Platform: |
Size: 188416 |
Author:称自己 |
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Description: 利用VHDL语言对FPGA进行锁相环倍频，经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency Platform: |
Size: 361472 |
Author:huangshaobo |
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Description: 分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE Platform: |
Size: 9427968 |
Author:DMANO |
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Description: 基于EP2C8的锁相环倍频文件 原来时钟为25Mhz 倍频为100Mhz-File the original clock of the EP2C8 the phase locked loop frequency multiplier 25Mhz for 100Mhz Platform: |
Size: 384000 |
Author:Young |
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Description: 分频选择系统。inclk0端输入25MHz信号，通过altpll倍频为400MHz信号C0端输出，需求不一样自己改倍频器参数。分频器clkdiv用来二分频、四分频、八分频、十六分频，分别分频为200MHz、100MHz、50MHz、25MHz四种频率信号输入到选择器中。选择器的TCLK是外部输入信号，A[3..0]是四个独立按键，选择器是用按键的不同组合来从四个分频喜好和一个TCLK中选择一路输出。代码清晰易懂，不符合需求请自行扩展-Frequency selection system. the inclk0 side input 25MHz signal, multiplier by altpll at 400MHz signal C0-ended output, demand not the same as their own to change the parameters of frequency multiplier. The divider clkdiv used divided by two, divide-eighth of the frequency, and 16 divided by, respectively, are at a frequency of 200MHz, 100MHz, 50MHz, 25MHz four kinds of frequency signals input to the selector. Select the TCLK is an external input signal, A [3 .. 0] four separate buttons, selector all the way to the output with a different combination of buttons to choose from the four sub-frequency preferences and TCLK. Code is clear and easy to understand, does not meet the needs of your own expansion Platform: |
Size: 347136 |
Author:lcl |
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Description: 一个完整的已经过测量和验证的VHDL程序，测量范围从1Hz到1GHz的频率计，也可以当做计数器，通过LCD1602显示频率值，四路独立按键可以控制输出不同的频率值、控制对应的独立LED亮灭、控制蜂鸣器发声。输入的晶振频率是25MHz,不符合请自行在倍频器中更改参数。-Has been a complete VHDL program measurement and verification, measurement range from 1Hz to 1GHz frequency counter can be used as a counter LCD1602 displays frequency value, the four separate buttons can control the output frequency value, the control corresponds to an independent LEDlight off, control the buzzer. The input crystal frequency is 25MHz, does not meet your own to change the parameters in the frequency multiplier. Platform: |
Size: 1100800 |
Author:lcl |
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Description: 针对锁频锁相器( Phase and Frequency Detector, PFD) 应用于低信噪比、大频偏的条件, 通过理论分析和仿真验证阐述了窗口类型对系统频偏捕获速度、范围、噪声门限及相位噪声抖动的影响机理. 推导出等效相位噪声功率谱密度的表达式. 证明了大窗口具有更低的噪声门限和更小的稳态相位抖动, 但捕获速度较慢. 为了提高捕获速度, 对鉴相器输出值取极性运算得到改进的PFD 算法. 新算法不仅能增加鉴相增益提高捕获速度 还可以减少等效噪声功率谱密度降低相位抖动 同时新算法不需要乘法器便于硬件实现. 最后新算法的性能通过仿真得到了验证.-For frequency-locking phase-locked (Phase and the Frequency Detector PFD) conditions applied to the low signal to noise ratio, frequency offset, through theoretical analysis and simulation described the capture speed of the window type, the system frequency deviation, range, noise threshold and phase noise jitter mechanism. equivalent phase noise power spectral density expression is derived to prove the large windows with a lower noise threshold and the steady-state phase jitter, but to capture slow in order to improve the capture speed, The phase detector output value to take the polarity operator improved PFD algorithm. new algorithm not only can increase the phase gain to improve the capture speed can also reduce the equivalent noise power spectral density to reduce the phase jitter new algorithm does not require a multiplier to facilitate hardware implementation performance of the last new algorithm has been verified through simulation. Platform: |
Size: 466944 |
Author:jing |
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Description: DDS开发基本原理 基于查询相位的倍频器-DDS to develop basic principle is based on the query phase frequency multiplier Platform: |
Size: 584704 |
Author:高星冉 |
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Description: 基于DSP6713，对DSP内的锁相环相关的寄存器进行设置，实现锁相环倍频功能，DSP入门级资料。-Based on the DSP6713, the DSP phase-locked loops in the relevant register set, realization of PLL frequency multiplier function, DSP entry-level data. Platform: |
Size: 1184768 |
Author:李华 |
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Description: 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency multiplier Platform: |
Size: 1024 |
Author:wulei |
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Description: This work addresses the analysis of families of sound signals through linear transformations that map signals to each other. These transformations are modeled as Gabor multipliers, which are defined by point wise multiplication with a given transfer function in the time-frequency (i.e. Gabor) domain. New approaches for the estimation of such transfer functions, based upon regularized variational approaches are developed. The estimated transfer functions can be used for various purposes in signal analysis and processing. This paper describes an application to sound morphing, in which the regularization parameter plays the role of tuning parameter between input and output signals.
Platform: |
Size: 1605632 |
Author:noufan |
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Search - frequency multiplier