Search - fsm in fpga

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[Other resource] FSM_design_guide DL : 0: 在FPGA设计时常用到FSM设计,本文很好地指导如何设计FSM-in FPGA design often used FSM design, a good guide is how to design FSM
Update : 2008-10-13 Size : 212.33kb Publisher : zhangbijun
[Program doc] Designing State Machines for FPGAs DL : 0: Update : 2025-02-17 Size : 60kb Publisher : 周
[Software Engineering] FSM_design_guide DL : 0: 在FPGA设计时常用到FSM设计,本文很好地指导如何设计FSM-in FPGA design often used FSM design, a good guide is how to design FSM
Update : 2025-02-17 Size : 212kb Publisher : zhangbijun
[VHDL-FPGA-Verilog] yetert DL : 0: This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
Update : 2025-02-17 Size : 448kb Publisher : crion
[VHDL-FPGA-Verilog] rafal2 DL : 0: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Update : 2025-02-17 Size : 919kb Publisher : nukom
[VHDL-FPGA-Verilog] zhuangtaiji DL : 0: Update : 2025-02-17 Size : 949kb Publisher : 李军
[Software Engineering] AReconfigurableFIRFilterSystemBasedonFPGA DL : 0: 本文将FPGA的快速性和计算机的灵活性通过USB2．0总线有机地结合起来，设计了一个基于FPGA的可调参数FIR滤波系统。此系统由计算机根据各种滤波器指标计算出滤波参数，通过USB2．0对FPGA芯片内部的FIR多阶滤波器进行参数配置，实现数字滤波器参数可调；配置后的FPGA滤波单元完成对A／D采集的信号进行滤波运算，滤波后的数据经过缓存后通过USB2．0总线传输至计算机进行显示、分析和储存等进一步处理。在系统中采用有限状态机对FPGA参数配置模式和滤波模式进行切换，保证了系统的有序运行。-In this dissertation，a reconfigurable FIR filter system based on FPGA is designed，which combine high—speed operation of FPGA and flexibility of computer using USB2．0 interface．According to the filter specialties，the filter coefficients are calculated by the computer．And the configured coefficients of the multistage FIR filter are downloaded to the chip．The filtering computing is completed by the FPGA．The filtered data iS transmitted to the computer through the USB2．0 interface for further processing，such as displaying，analyzing and storing．The states conversion between coefficients configuring mode and filtering mode is finished by FSM(Finite State Machine)，which ensures the system to work orderly．
Update : 2025-02-17 Size : 6.08mb Publisher : mabeibei
[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte DL : 0: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Update : 2025-02-17 Size : 4.84mb Publisher : mabeibei
[VHDL-FPGA-Verilog] FSM DL : 0: 文章介绍的状态机的优化写法，并给出经典实例。使读者更清楚的明了FPGA中状态机的优点，以便工程中的使用。-This paper introduces the optimization of state machines written, and gives the classic example. So that readers understand more clearly the advantages of FPGA in the state machine to the project use.
Update : 2025-02-17 Size : 290kb Publisher : leo wong
[VHDL-FPGA-Verilog] mealy DL : 0: MEALY fsm source code in vhdl, implemented on fpga
Update : 2025-02-17 Size : 321kb Publisher : alyna
[VHDL-FPGA-Verilog] moore DL : 0: MOORE fsm source code in vhdl, implemented on fpga
Update : 2025-02-17 Size : 195kb Publisher : alyna
[VHDL-FPGA-Verilog] switch_rot DL : 0: switch rotator fsm for spartan 3 fpga in verolog leanguage
Update : 2025-02-17 Size : 181kb Publisher : Omar Pont
[Other Embeded program] FSM DL : 0: It is the FSM implemented in Xylinx 14.7 on FPGA
Update : 2025-02-17 Size : 316kb Publisher : Zaryab
[VHDL-FPGA-Verilog] simple FSM0 DL : 0: simple implemenation of FSM in VHDL
Update : 2025-02-17 Size : 3kb Publisher : allia
[VHDL-FPGA-Verilog] machine DL : 0: Simple finite state machine on Altera Cyclone II
Update : 2025-02-17 Size : 284kb Publisher : godup