Search - gf verilog

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[Other resource] rs_decoder_31_19_6.tar DL : 0: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15 * 21 ^ 6 a X * X ^ a ^ 15 2 * X ^ a ^ 3 25 * X ^ a ^ 4 17 5 * X ^ a ^ 18 ^ 6 X * a * X 30 ^ 7 ^ a ^ 20 * X ^ a ^ 23 8 * X ^ a ^ 9 * 27 X 10 ^ a ^ 24 * 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Date : 2008-10-13 Size : 13.91kb User : 孟轲敏
[Other resource] GFEMultiplierTaps DL : 0: 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序
Date : 2008-10-13 Size : 8.88kb User : ChenQiu
[Other resource] GFEConsMulTaps DL : 0: 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序
Date : 2008-10-13 Size : 7.87kb User : ChenQiu
[Other resource] GFEInvertor DL : 0: 用于生成GF(2^m)有限域元素求逆器的Verilog HDL源文件的C程序
Date : 2008-10-13 Size : 8.9kb User : ChenQiu
[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar DL : 1: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Date : 2025-07-03 Size : 14kb User : 许茹芸
[VHDL-FPGA-Verilog] GFEMultiplierTaps DL : 0: 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain Multiplier Verilog HDL source file of C program
Date : 2025-07-03 Size : 195kb User : ChenQiu
[VHDL-FPGA-Verilog] GFEConsMulTaps DL : 0: 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain constant multiplier Verilog HDL source files of C procedures
Date : 2025-07-03 Size : 168kb User : ChenQiu
[VHDL-FPGA-Verilog] GFEInvertor DL : 0: 用于生成GF(2^m)有限域元素求逆器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) finite field element inversion
Date : 2025-07-03 Size : 169kb User : ChenQiu
[VHDL-FPGA-Verilog] GFmultiply DL : 1: Verilog hdl语言伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Date : 2025-07-03 Size : 2kb User : 许立宾
[VHDL-FPGA-Verilog] Galois_field_multiplier_verilog_design DL : 0: 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
Date : 2025-07-03 Size : 2kb User : 海天之洲
[VHDL-FPGA-Verilog] mix DL : 0: 本代码是基于Verilog语言，是在伽罗瓦域GF(2^8)上完成加法和乘法运算，主要完成ASE加密的列混合运算-This code is based on the Verilog language, is the Galois field GF (2 ^ 8) on the completion of addition and multiplication, the main column of the completion of ASE encryption hybrid operation
Date : 2025-07-03 Size : 225kb User : 钟佳荣
[VHDL-FPGA-Verilog] chengfaqi DL : 0: 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
Date : 2025-07-03 Size : 2kb User : 李永超
[VHDL-FPGA-Verilog] RS(204-188)decoder_verilog DL : 0: 采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}-Verilog achieved using the finite field GF (28) weak dual basis multiplier
Date : 2025-07-03 Size : 14kb User : 刘建涛
[VHDL-FPGA-Verilog] RS DL : 0: 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)
Date : 2025-07-03 Size : 3.68mb User : heyu7892020
[Crack Hack] AES-GF(2^4)^2 for sbox DL : 0: AES加解密程序，128bit数据位宽，其中sbox和混合列运算在复合域GF(2^4)^2上完成(An AES encryption and decryption program with 128 bits datawidth, which used GF(2^4)^2 for sbox and mixcolumn.)
Date : 2025-07-03 Size : 17kb User : 酱瓶
[VHDL-FPGA-Verilog] GF乘法器 DL : 0: 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
Date : 2025-07-03 Size : 1kb User : 未曾走远