Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder Platform: |
Size: 1024 |
Author:韩善华 |
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Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder Platform: |
Size: 1024 |
Author:韩善华 |
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Description: 数字钟的程序，功能说明如下所示：
1.完成秒／分／时的依次显示并正确计数；
2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位；
3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时；
4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整
5.可以选择使用12进制计时或者24进制计时。
使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。
-Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above. Platform: |
Size: 232448 |
Author:余宾客 |
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Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as Platform: |
Size: 82944 |
Author:lkiwood |
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Description: How to transform a binary 4 digit number into a 8 bit number for a seven segment display, characters 0 to 15 i.e. Hexadecimal. Platform: |
Size: 313344 |
Author:Basil |
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Description: 这是一段用VHDL语言写的24进制计数器，用数码管显示，我用了例化语句，分为24进制计数器模块，十位译码，个位译码，用cycloneII ep2系列实验板验证，能计数0~23。此程序还可以修改为100以内任何进制计数器。-This is a written in VHDL language 24 a binary counter, using digital tube display, I used the instantiated statements, divided into 24 hexadecimal counter module, ten decoding, decoded bits, with cycloneII ep2 series experiment validation, can count 0 ~ 23. This program can also be modified to 100 within any binary counter.
Platform: |
Size: 353280 |
Author:高安 |
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