Description: 基于FPGA的I2C总线模拟,采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation. Platform: |
Size: 204800 |
Author: |
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Description: Verilog语言的I2C总线,完整的模拟。适合做FPGA开发。-Verilog language I2C bus, a complete simulation. Suitable for FPGA to do the development. Platform: |
Size: 702464 |
Author:雷虎宝 |
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Description: 用verilog设计了一个简洁而实用的I2C总线控制器,对大家学习FPGA和I2C总线接口等相关方面的知识有较大的帮助。-Verilog design using a simple and practical I2C bus controller, for everyone to learn FPGA and I2C bus interface and other related knowledge has a greater help. Platform: |
Size: 522240 |
Author:郑玮 |
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Description: I2C最经典的技术文档集合,包括了总线规范、协议、设计应用。-I2C most classic collection of technical documentation, including a bus norms, protocols, design applications. Platform: |
Size: 2480128 |
Author:江望明 |
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Description: FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.-FPGA EP2C5Q288C8 I2C original code, test that is used to open OK. Platform: |
Size: 831488 |
Author:kenychen |
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Description: FPGA开发板配套Verilog代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board supporting Verilog code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications. Platform: |
Size: 3393536 |
Author:chenlu |
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Description: I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This module is written with Verilog HDL and has been tested on a Cyclone II FPGA Platform: |
Size: 6144 |
Author:magic_andy |
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Description: This document serves as an example based tutorial to programming the Spartan 3 FPGA included in your parts kit using Xilinx ISE Tools. A Basic working knowledge of how to create schematics in Xilinx is required.
The Spartan 3 FPGA can be programming directly from the Xilinx ISE package, greatly simplifying and expediting the design process. Programming the FPGA using a schematic, state diagram, or verilog module is a universally simple and straightforward process. Platform: |
Size: 253952 |
Author:Mohamed Saleh |
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