Search - i2c rtl

[VHDL-FPGA-Verilog] i2c.tar

Description: 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
Platform: | Size: 702464 | Author: 杨力 | Hits:

[Embeded-SCM Develop] i2c

Description: i2c rtl code , document, simulation
Platform: | Size: 740352 | Author: andy | Hits:

[ELanguage] i2c_master_slave_latest[1].tar

Description: I2C Core VHDL RTL Source Code for Synthesis
Platform: | Size: 3072 | Author: tan | Hits:

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:

[VHDL-FPGA-Verilog] i2c

Description: I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
Platform: | Size: 13312 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] i2c

Description: I2C的RTL源码，verilog，验证过的-I2C verilog RTL
Platform: | Size: 89088 | Author: zhangq | Hits:

[VHDL-FPGA-Verilog] I2C_Verilog_Model

Description: 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
Platform: | Size: 364544 | Author: jinjin | Hits:

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[VHDL-FPGA-Verilog] i2c.tar

[Embeded-SCM Develop] i2c

[ELanguage] i2c_master_slave_latest[1].tar

[Other] yuqix_datum

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] I2C_Verilog_Model

[Editor] i2c_testbench

[VHDL-FPGA-Verilog] i2c_master

[VHDL-FPGA-Verilog] i2c_slave

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