Description: 本示例中使用了一个DCM模块，将输入时钟50MHz，倍频到100MHz，分频到25MHz，不同的频率值通过LED进行演示。-This example uses a DCM module, the input clock 50MHz, frequency-doubled to 100MHz, frequency to 25MHz, the frequency of different values demonstrated through the LED. Platform: |
Size: 631808 |
Author:沈天平 |
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Description: verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second Platform: |
Size: 1024 |
Author:lvlv |
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Description: 使用verilog编写的模块，输出1080p彩条测试视频，输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M) Platform: |
Size: 1024 |
Author:星沉大海
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Description: 题目1：设计一个8位数字显示的简易频率计。要求：
①能够测试10Hz~10MHz方波信号；
②电路输入的基准时钟为1Hz，要求测量值以8421BCD码形式输出；
③系统有复位键；
④采用分层次分模块的方法，用Verilog HDL进行设计。
⑤写出测试仿真程序(Topic 1: Design a simple frequency meter with 8 digits display. Requirement:
It can test 10 Hz ~ 10 MHz square wave signal.
(2) The reference clock input by the circuit is 1Hz, which requires the measured value to be output in the form of 8421BCD code.
(3) The system has reset keys;
(4) The design is based on Verilog HDL with the method of hierarchical module.
Write out the test simulation program) Platform: |
Size: 140288 |
Author:鹏jjjjj |
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Search - input frequency module verilog