Description: verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
- [my_design_frequency] - in digital circuits, and often the need
- [ADC0809] - Sequential Circuits adc0809 the FPGA int
- [eternityclock] - Write their own extensions clock, an inc
- [div] - VHDL arbitrary integer frequency procedu
- [ps2_mouse] - ps2 mouse driver
- [6.5fenpin] - fen pin qi
- [zz] - Keying increase/decrease counter to 20MH
- [verilogfenpinqi] - divider verilog code for multiple sub-di
- [VEDA7LED] - By QUARTUS II 7.2 (32-BIT) tools to achi
- [Clk50M_div_1HZ] - Clk50M_div_1HZ, using counter this study
File list (Check if you may need any files):
50M分频器
.........\DIV_50M_HZ.bsf
.........\DIV_50M_HZ.v