Description: By QUARTUS II 7.2 (32-BIT) tools to achieve the two 7-segment digital tube dynamic scan showed the VHDL program. 8-bit hardware with dial-bit switch control, high control left four digital control, control of the right fourth digital control. Chip EP1C6T144FPGA device.
To Search:
- [DTXS] - Verilog HDL, prepared by four digital tu
- [50M] - verilog language sub-frequency module, u
File list (Check if you may need any files):
VEDA7LED动态扫描\db\dtled.asm.qmsg
................\..\dtled.cbx.xml
................\..\dtled.cmp.bpm
................\..\dtled.cmp.cdb
................\..\dtled.cmp.ecobp
................\..\dtled.cmp.hdb
................\..\dtled.cmp.logdb
................\..\dtled.cmp.rdb
................\..\dtled.cmp.tdb
................\..\dtled.cmp0.ddb
................\..\dtled.cmp_bb.cdb
................\..\dtled.cmp_bb.hdb
................\..\dtled.cmp_bb.logdb
................\..\dtled.cmp_bb.rcf
................\..\dtled.dbp
................\..\dtled.db_info
................\..\dtled.eco.cdb
................\..\dtled.eds_overflow
................\..\dtled.fit.qmsg
................\..\dtled.fnsim.hdb
................\..\dtled.fnsim.qmsg
................\..\dtled.hier_info
................\..\dtled.hif
................\..\dtled.map.bpm
................\..\dtled.map.cdb
................\..\dtled.map.ecobp
................\..\dtled.map.hdb
................\..\dtled.map.logdb
................\..\dtled.map.qmsg
................\..\dtled.map_bb.cdb
................\..\dtled.map_bb.hdb
................\..\dtled.map_bb.logdb
................\..\dtled.merge_hb.atm
................\..\dtled.pre_map.cdb
................\..\dtled.pre_map.hdb
................\..\dtled.psp
................\..\dtled.pss
................\..\dtled.rpp.qmsg
................\..\dtled.rtlv.hdb
................\..\dtled.rtlv_sg.cdb
................\..\dtled.rtlv_sg_swap.cdb
................\..\dtled.sgate.rvd
................\..\dtled.sgate_sm.rvd
................\..\dtled.sgdiff.cdb
................\..\dtled.sgdiff.hdb
................\..\dtled.signalprobe.cdb
................\..\dtled.sim.cvwf
................\..\dtled.sim.hdb
................\..\dtled.sim.qmsg
................\..\dtled.sim.rdb
................\..\dtled.simfam
................\..\dtled.sld_design_entry.sci
................\..\dtled.sld_design_entry_dsc.sci
................\..\dtled.syn_hier_info
................\..\dtled.tan.qmsg
................\..\dtled.tis_db_list.ddb
................\..\mux_1hc.tdf
................\..\prev_cmp_dtled.asm.qmsg
................\..\prev_cmp_dtled.fit.qmsg
................\..\prev_cmp_dtled.map.qmsg
................\..\prev_cmp_dtled.sim.qmsg
................\..\prev_cmp_dtled.tan.qmsg
................\..\prev_cmp_leddongtai.qmsg
................\..\wed.wsf
................\dtled.asm.rpt
................\dtled.done
................\dtled.dpf
................\dtled.fit.rpt
................\dtled.fit.smsg
................\dtled.fit.summary
................\dtled.flow.rpt
................\dtled.map.rpt
................\dtled.map.summary
................\dtled.pin
................\dtled.pof
................\dtled.qsf
................\dtled.sim.rpt
................\dtled.sof
................\dtled.tan.rpt
................\dtled.tan.summary
................\dtled.vhd
................\dtled.vhd.bak
................\dtled.vwf
................\leddongtai.qpf
................\leddongtai.qws
................\ledpll.cmp
................\ledpll.ppf
................\ledpll.vhd
................\ledpll_inst.vhd
................\ledpll_waveforms.html
................\redeme.txt
................\sopc_builder_log.txt
................\新建文件夹\ledpll.cmp
................\..........\ledpll.ppf
................\..........\ledpll.vhd
................\..........\ledpll_inst.vhd
................\..........\ledpll_wave0.jpg
................\..........\ledpll_waveforms.html
................\..........\mypllclk.cmp
................\..........\mypllclk.ppf
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