Description: 基于FPGA的B超数据采集功能，根据输入图像的束同步与帧同步信号，采用中断控制进入FIFO的图像数据的读写操作！-FPGA-based B-data collection capabilities, according to the input image beam synchronization and frame synchronization signal used to control access to FIFO interrupt the operation of image data read and write! Platform: |
Size: 3072 |
Author:齐磊 |
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Description: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288).
Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions. Platform: |
Size: 3416064 |
Author:Bill Guan |
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Description: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co Platform: |
Size: 868352 |
Author: |
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Description: 使用fpga开发图像处理时往往会遇到各种困难，调试周期比较长，尤其是输入输出接口。但我们想先研究算法，所以这里给出了一个工具，可以帮助我们实现这个功能。这个工具作为辅助工具，算法实现部分可以通过modelsim来完成-Image processing using fpga development often will encounter various difficulties, debug cycle is relatively long, especially input and output interfaces. But we would like to study algorithms, so here is a tool that can help us to achieve this functionality. This tool as an auxiliary tool, the algorithm can achieve some modelsim to complete Platform: |
Size: 2034688 |
Author:zhaojkun |
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Description: 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display. Platform: |
Size: 2547712 |
Author:chenxin |
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Description: 使用视频板上FPGA——EP3C16F484C6（Altera-CycloneⅢ），以及与FPGA相连的视频信号转换芯片SiI7171和SiI7170芯片。 图像信号由计算机通过SiI7171输入至FPGA，在FPGA 上进行图像信号Gamma变换图像处理（γ 1.0, γ 2.5, γ 2.8）之后，再通过上路SiI7170输出到显示器显示。-Using the video board FPGA- EP3C16F484C6 (Altera-Cyclone Ⅲ), and connected with the FPGA video signal conversion chip SiI7171 and SiI7170 chip. The image signal is input to the FPGA through the SiI7171 computer, and the image signal Gamma transform image processing (γ 1.0, γ 2.5, γ 2.8) is carried out on the FPGA, and then output to the display through the SiI7170. Platform: |
Size: 5509120 |
Author:Alice_Ecnu |
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Description: A fast connected component labeling algorithm based on FPGA is presented for high speed image processing
on the condition that the images are continuous without horizontal blanking. Using run length code to optimize image
labeling, the labels’number and length of equivalent table can be reduced. And the component’s features can also be
extracted during run length coding. Then using the way of scanning every pixel, the connected labels can be linked in a
single clock period. Finally the labels and features are merged in the procedure of equivalent table combination. The FPGA
simulation results indicate that, when connected component labeling and features extraction for a continuous binary image
are in progress, the processing time just includes the image input time and the equivalents table combination time. It is
more efficient than others and suitable for fast image recognition and tracking Platform: |
Size: 2195456 |
Author:杨松 |
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Search - input image to FPGA