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[Windows Develop] cpu16 DL : 0: 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic unit (ALU), memory read and write (MEM) and Write Back (WB).
Update : 2025-02-17 Size : 6kb Publisher : 周健
[Embeded-SCM Develop] REG89LPx052 DL : 0: Include file for ATMEL AT89LPx052 MCS-51 base instruction on enhanced CPU core that can fetch a single byte from memory every clock cycle, So may faster than classic 8051 architecture 6 to 12 times. These .h define SFR that not available in any other C51.h. Such, P1M0, P1M1, P3M0 and P3M1 for configure port function that not avail ever.before.
Update : 2025-02-17 Size : 1kb Publisher : Manorat BOON-AUR
[Windows Develop] Bochs_Analysis DL : 0: 这是bochs虚拟机内部的源代码的分析，只涉及到cpu的部分，包括取指，译指，指令执行等，希望对大家有用。-This is a virtual machine inside the bochs source code analysis, only the part related to the cpu, including fetch, translated means, instruction execution, and I hope useful.
Update : 2025-02-17 Size : 755kb Publisher : 胡涛
[Windows Develop] OTA_TARGET_V2.2 DL : 0: First, the CPU must make access memory to fetch the instruction. The instruction contains the address of the data we want to load. During the execute phase accesses memory to load the data value located at that address for a total of two trips to memory
Update : 2025-02-17 Size : 444kb Publisher : so
[VHDL-FPGA-Verilog] zxcpu DL : 0: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Update : 2025-02-17 Size : 1.03mb Publisher : zhaoshu
[VHDL-FPGA-Verilog] 1_instruction_fetching DL : 0: Risc processor :- Instruction fetch code
Update : 2025-02-17 Size : 5kb Publisher : mahesh
[VHDL-FPGA-Verilog] RISC_CPU DL : 0: 1. RISC工作每执行一条指令需要八个时钟周期。RISC的复位和启动通过rst控制，rst高电平有效。Rst为低时，第一个fetch到达时CPU开始工作从Rom的000处开始读取指令，前三个周期用于读指令。在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备对总线写操作时，在第3.5个时钟周期处，建立写的地址，第4个时钟周期输出数据，第5个时钟周期输出写信号。至第6个时钟结束，第7.5时钟地址输出PC地址，为下一个指令周期做好准备。 2. 操作过程：新建工程，编译compile all，然后仿真，在wave窗口加入要观察的信号，然后run –all，结束时完成test1的测试，重复两次run –all完成test2，test3的波形仿真。 -1. RISC work every eight clock cycles to execute an instruction needs. RISC reset and start by rst control, rst active high. Rst is low, the first CPUs fetch arrives starting from Rom s 000 start reading instruction, the first three cycles for reading instruction. When the read operation is performed on the bus, at 3.5 cycles, memory, or port address output to the address bus, 4- 6 clock cycles, and the read signal rd, read data to the bus, a logic operation. 7 clock cycles, rd invalid, 7.5 PC clock address output address, ready for the next instruction The write operation on the bus, in Section 3.5 of the clock cycle, to establish a write address, and four clock cycles and output data, the fifth clock cycle output write signal. To the end of the six clock the 7.5 clock address output PC address, ready for the next instruction cycle. Operation: new construction, the compiler compile all, and simulation, join in the wave window to observe the signal, then the run-all completed by the
Update : 2025-02-17 Size : 1002kb Publisher : 宋颖
[VHDL-FPGA-Verilog] IFCtrl.v DL : 0: dlx design的if模块，instruction fetch，stage 1-dlx design of if module, instruction fetch, stage 1
Update : 2025-02-17 Size : 1kb Publisher : Jeff
[e-language] cpuqu DL : 0: 易语言汇编取cpu信息源码例程程序使用汇编指令取cpu制造商、是否支持mmx指令，是否支持sse指令。本易语言源码例程属于易语言高级教程。点评：易语言汇编取cpu信息源码仅供学习参考。-Easy language assembler routines take cpu source program using the assembler instruction fetch cpu manufacturer support mmx instruction, whether to support sse instruction. The easy language source code routines are easy language and advanced tutorials. Comments: Easy to take cpu assembler language source Study reference only.
Update : 2025-02-17 Size : 2kb Publisher : 雪欣
[Successful incentive] main DL : 0: My file is about Fetch and Executive stages of processing. The processor contains a single data register, called the accumulator (AC). Both instructions and data are 16 bits long, and memory is organized as a sequence of 16-bit words. The instruction format provides 4 bits for the opcode,allowing as many as 24 16 different opcodes (represented by a single hexadecimal3 digit). The opcode defines the operation the processor is to perform.With the remaining 12 bits of the instruction format,up to 212 4096 (4 K) words of memory (denoted by three hexadecimal digits) can be directly addressed.
Update : 2025-02-17 Size : 1kb Publisher : Diana
[Software Engineering] CPU_design_Example DL : 0: 设计的CPU字长为16位，可以实现子程序调用，分支，循环及各种算术逻辑运算等功能。访存的指令采用寄存器间址寻址(R)或是基址寻址X(R)实现， -Design CPU 16 word length can be achieved subroutine calls, branches, loops, and various arithmetic and logical operations and other functions. Between instruction fetch register using indexed addressing (R) Based addressing or X (R) implementation,
Update : 2025-02-17 Size : 437kb Publisher : 赵安