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[VHDL-FPGA-Verilog] suij

Description: 硬件编程实现伪随机交织器和随机交织器，应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
Platform: | Size: 2048 | Author: 孟旭 | Hits:

[GDI-Bitmap] verilog_interleave1

Description: 里面是5个关于交织器的源代码，有兴趣的可以下来学习一下-There is a 5 on the interleaver of the source code, are interested in learning what can be down
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[VHDL-FPGA-Verilog] veriloginterleave2

Description: 交织器的在5个源代码，:-) 对学习交织器真的很有用的啊 -Interleaver in 5 source code, :-) learning interleaver ah really useful
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[VHDL-FPGA-Verilog] interleave

Description: 数据交织器 verilog HDL源文件-Data interleaver verilog HDL source file
Platform: | Size: 100352 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
Platform: | Size: 27648 | Author: 尚龙 | Hits:

[Other] FPGA_interleaver

Description: 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
Platform: | Size: 120832 | Author: xx | Hits:

[VHDL-FPGA-Verilog] interweave_1

Description: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
Platform: | Size: 36864 | Author: 李修函 | Hits:

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