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[VHDL-FPGA-Verilog] deinterlace

Description: Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
Platform: | Size: 99328 | Author: cloud | Hits:

[VHDL-FPGA-Verilog] bbb

Description: AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.
Platform: | Size: 216064 | Author: sss | Hits:

[Other] hbf

Description: 在软件无线电中半带滤波器的设计与实现，半带滤波器实现的是2的幂次的抽取或插值。 -In software radio half-band filter design and realization of half-band filter is the realization of 2-power extraction or interpolation.
Platform: | Size: 246784 | Author: 岑楠 | Hits:

[VHDL-FPGA-Verilog] cic

Description: verilog码写的CIC滤波器的程序，包括4倍抽取CIC滤波器和内插的CIC滤波器两个-Verilog code written by CIC filter procedures, including 4 times the extraction CIC filter and the CIC interpolation filter two
Platform: | Size: 22528 | Author: 桃子 | Hits:

[SCM] cic1s2

Description: 单级CIC2倍内插滤波器，用verilogHDL实现-CIC2 times the single-stage interpolation filter, used to achieve verilogHDL
Platform: | Size: 498688 | Author: Carl | Hits:

[VHDL-FPGA-Verilog] hbf

Description: 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
Platform: | Size: 18432 | Author: pll | Hits:

[VHDL-FPGA-Verilog] baseband_verilog

Description: verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器-verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
Platform: | Size: 26624 | Author: 刘新 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
Platform: | Size: 4096 | Author: 张霄 | Hits:

[VHDL-FPGA-Verilog] myinterpolation

Description: 复杂的插值函数，用于颜色空间转换 verilog-The complex interpolation function for color space conversion verilog
Platform: | Size: 1024 | Author: zhangxinggang | Hits:

[VHDL-FPGA-Verilog] cic_intp_64_four

Description: 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
Platform: | Size: 1024 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] DDA_xy

Description: 运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。-Verilog language using digital integration method, the X axis and Y axis interpolation operations.
Platform: | Size: 1218560 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] mc_t

Description: 利用verilog实现H.264中半像素插值功能。30个周期完成一个4x4块儿的横向、纵向和斜向的插值。-Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
Platform: | Size: 17296384 | Author: 吴汶泰 | Hits:

[VHDL-FPGA-Verilog] resolutionquartusII

Description: 用verilog编写的分辨率提高的源代码 采用双线性插值-Written resolution with the verilog source code to improve the use of bilinear interpolation
Platform: | Size: 6241280 | Author: 权晶 | Hits:

[VHDL-FPGA-Verilog] interpolation-filer-rtl

Description: synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
Platform: | Size: 3072 | Author: swordever | Hits:

[VHDL-FPGA-Verilog] CIC-UPSAMPLE

Description: CIC内插 内插系数可变，阶数1~6,Verilog版本-Inserted within the CIC interpolation factor variable, the order of 1 to 6, the Verilog version
Platform: | Size: 3072 | Author: 邹燕然 | Hits:

[Special Effects] video_stream_scaler

Description: Verilog HDL实现双线性插值视频实时缩放，源码及说明文档-Verilog HDL bilinear interpolation real-time zoom, video source and documentation
Platform: | Size: 5643264 | Author: | Hits:

[Special Effects] color-interpolation

Description: 用verilog实现的颜色插值，有带仿真-Color interpolation using verilog realize there with simulation
Platform: | Size: 5120 | Author: 吴火森 | Hits:

[VHDL-FPGA-Verilog] interpolate4

Description: 调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
Platform: | Size: 1024 | Author: 右下角 | Hits:

[Other] control_s

Description: 数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
Platform: | Size: 4925440 | Author: qing wang | Hits:

[Special Effects] interpolation

Description: 图像线性插值Verilog代码，已通过FPGA验证(Image linear interpolation Verilog code, has been verified by FPGA)
Platform: | Size: 5120 | Author: pweorpenguin | Hits:
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