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[Other Embeded program] epp_sram

Description: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send interrupt signals to interrupt the process of writing to read the data in the SRAM. rar package includes epp agreement, modules and test documents (test).
Platform: | Size: 43008 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] rxd

Description: 自己编写的串口UART的接收Verilog模块，支持中断和查询方式接收，对信号的畸变适应能力强。-I have written serial UART reception Verilog modules, support and inquiries receive interrupt signal distortion adaptable.
Platform: | Size: 2048 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] FPGA_jiaocheng_yu_shiyan

Description: 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-The most important thing is seven from simple to complex experiments, including: the basis of the experimental basis for a _FPGA_LED experiment II _seg7 the basis of experiment and simulation experiments based on three experiments _SOPC_LED programmer _Flash the basis of four experiments of five experiments _ timer six experimental basis _ keys, as well as experimental experimental PIO interrupt I _ 7 card use, these laboratories used the SOPC BUILDER with NOIS ii, the use of Verilog to prepare, there are no experimental test panels and plates can be used to learn. The second also includes: FPGA development board of the links between memory, multi-processor documents, USB_UART such as documents, useful documents, you will not regret it a sure!
Platform: | Size: 6065152 | Author: yuezhiying_007 | Hits:

[VHDL-FPGA-Verilog] sourcefile

Description: 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序，希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序，对应四个按键，按其中任何一个键都可以发送一个中断； keyint.c是Nios中编写的C程序，用于检测按键的中断，如果检测到中断，会检测是哪个按键按下，从而执行相应的程序！ -In Altera' s Cyclone series FPGA development board interrupt key test procedures, interruption of hope to those who study the development of help for beginners. verilog prepared pio_key.v button is interrupted procedures, corresponding to the four keys, in accordance with any one key can send an interrupt keyint.c is prepared Nios of C procedures for detecting the interruption of keys, if the interruption is detected, will detect which button is depressed, thus the implementation of appropriate procedures!
Platform: | Size: 3072 | Author: 王陶 | Hits:

[VHDL-FPGA-Verilog] simple_pic

Description: 一个通用中断系统的Verilog HDL描述，对想了解知道是怎么实现的读者，可以查看综合出来的电路，会有很大帮助！-A common interrupt system of the Verilog HDL description of the would like to know how to achieve the readers know, there will be of great help!
Platform: | Size: 446464 | Author: 陈永恒 | Hits:

[VHDL-FPGA-Verilog] _8259A

Description: 　 8259A是专门为了对8085A和8086/8088进行中断控制而设计的芯片，它是可以用程序控制的中断控制器。单个的8259A能管理8级向量优先级中断。在不增加其他电路的情况下，最多可以级联成64级的向量优先级中断系统。8259A有多种工作方式，能用于各种系统。各种工作方式的设定是在初始化时通过软件进行的。 在总线控制器的控制下,8259A芯片可以处于编程状态和操作状态.编程状态是CPU使用IN或OUT指令对8259A芯片进行初始化编程的状态- 8259A is designed to be on the 8085A and 8086/8088 designed to interrupt control chip, which is the interrupt controller can be programmed. 8259A can manage a single priority interrupt vector 8. Without increasing the other circuit cases, up to 64-level cascaded priority interrupt system vector. 8259A there are several methods of work, can be used in a variety of systems. A variety of work settings is carried out by software initialization. Under the control of the bus controller, 8259A chip can be programmed at the state and operating state. Programming state is CPU use IN or OUT instruction program on the 8259A chip, to initialize the state of
Platform: | Size: 764928 | Author: keven | Hits:

[VHDL-FPGA-Verilog] c432

Description: verilog coding for 36 bit interrupt controller
Platform: | Size: 4096 | Author: Goluguri reddy | Hits:

[VHDL-FPGA-Verilog] PRIORITY_ENCODER

Description: A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority request. If two or more inputs are given at the same time, the input having the highest priority will take precedence. An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output since it is superseded by higher-priority input.
Platform: | Size: 109568 | Author: swapnil | Hits:

[VHDL-FPGA-Verilog] 20104169105873879

Description: 主要功能：pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言，使用器件是Cyclone2，应用于其他FPGA时，直接调整管脚即可。-Main features: pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at regular intervals, resulting in increased data 1,2,3, etc., with pci9054 driver and application data to be transmitted 2. Description: The folder is Quartus 9.0 project file, use the Verilog language, the use of the device is Cyclone2, When applied to other FPGA, you can directly adjust the pins.
Platform: | Size: 4149248 | Author: | Hits:

[VHDL-FPGA-Verilog] Counter.v

Description: Custom verilog code for up counter with Interrupt.
Platform: | Size: 1024 | Author: Moganeshwaran | Hits:

[VHDL-FPGA-Verilog] ADSP2011Local

Description: pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at regular intervals, resulting in increased data 1,2,3, etc., with pci9054 drivers and applications for data transmission 2 note: folders is Quartus 9.0 project file, use the Verilog language.
Platform: | Size: 4899840 | Author: | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[VHDL-FPGA-Verilog] uart_1203_4

Description: MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, online similar material is few, most reference value! Provide only verilog source!
Platform: | Size: 2239488 | Author: 李康 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. Enhancements to the original interface include a wider supported operating frequency range, 4 entries deep read and write FIFOs, and programmable transfer count dependent interrupt generation. The high compatibility with the M68HC11 SPI port ensures that existing software can use this core without major modifications. New software can use existing examples as a starting point. The core features an 8 bit wishbone interface.
Platform: | Size: 49152 | Author: 邓楠 | Hits:

[VHDL-FPGA-Verilog] cpu_cache_interrupt

Description: verilog写的CPU 五级流水 带cache 中断-the the CPU five water with verilog to write cache interrupt
Platform: | Size: 49152 | Author: 王久力 | Hits:

[VHDL-FPGA-Verilog] Zet-1.3.1

Description: 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 interface .)
Platform: | Size: 2487296 | Author: VectorIII | Hits:

[VHDL-FPGA-Verilog] apb.v

Description: AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
Platform: | Size: 805888 | Author: 卧室一条鱼 | Hits:

[VHDL-FPGA-Verilog] xuartps_intr_example

Description: microblaze uart vivado(vivado microblaze interrupt)
Platform: | Size: 4096 | Author: xilinxer | Hits:

[Other] Interrupt_Controller-master

Description: Interrupt Controller Verilog
Platform: | Size: 21504 | Author: Tan Nguyen | Hits:

[VHDL-FPGA-Verilog] uart_55x_lite

Description: 本模块设计仿照ST16C554芯片，特点如下： a) Localbus总线接口； b) 多通道设计，最大通道数为4，实际通道数可配置； c) 两种中断方式，支持电平中断、沿中断；(The module is designed and modeled on ST16C554 chip. A) Localbus bus interface; B) multi-channel design. The maximum number of channels is 4, and the number of actual channels is configurable. C) two interrupt modes, supporting level interruption and interruption.)
Platform: | Size: 35840 | Author: fengyuanzyt | Hits:
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