Search - ip fir

[VHDL-FPGA-Verilog] Example-b4-2

Description: Altera IP应用设计实例  “\Example-b4-2\Project”目录下为设计工程  “\Example-b4-2\Solution”目录下为正确的解决方案，仅供读者参考 -Altera IP Application Design
Platform: | Size: 394240 | Author: king | Hits:

[VHDL-FPGA-Verilog] AltrFir32

Description: 借助于altera公司的IP核，在FPGA中使用dspbuilder实现32位低通FIR滤波器功能，-Altera With the company
Platform: | Size: 9216 | Author: 齐磊 | Hits:

[VHDL-FPGA-Verilog] niosII_cyclone_1c20

Description: IIR、F FT各模块程序设计例程，可做为IP使用，初学者很有用-IIR, FIR, FFT modular design of the routines can be used as IP use, useful for beginners
Platform: | Size: 70656 | Author: 石林 | Hits:

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[matlab] filter

Description: 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
Platform: | Size: 268288 | Author: xueanxi | Hits:

[DSP program] myfir

Description: 利用fir滤波器ip-core设计滤波器，数据为16bit，速率为61.44mhz，工作时钟为245.76mhz-The use of fir filter ip-core design of filters, the data for the 16bit, rate 61.44mhz, working clock 245.76mhz
Platform: | Size: 1024 | Author: 王丽 | Hits:

[Software Engineering] ISE_IP_FIR_FPGA

Description: 利用ISE的IP核在FPGA上设计fir滤波器-Fir filter IP core on FPGA design using the ISE
Platform: | Size: 101376 | Author: ACER | Hits:

[VHDL-FPGA-Verilog] signal-fir

Description: FPGA实现FIR滤波器，对信号的滤波处理，其中I用IP核实现数据的存储核-Based on the IP core of FPG, realize FIR filter design
Platform: | Size: 196608 | Author: 赵龙贺 | Hits:

[VHDL-FPGA-Verilog] COSTAS_LOOP

Description: 使用ISE12.1编写的Costas环，用于载波恢复，直接使用了IP核中的FIR和DDS模块-Use ISE12.1 written Costas loop for carrier recovery, the direct use of the IP core of FIR and DDS module
Platform: | Size: 1024 | Author: nike | Hits:

[VHDL-FPGA-Verilog] fir_test01

Description: 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
Platform: | Size: 1510400 | Author: xuegamgma | Hits:

[Other] fft

Description: 利用快速傅里叶变换FFT的ip核和fir的ip核制作的自适应滤波器-use fft ip and fir ip to make a Adaptive Filter
Platform: | Size: 413696 | Author: 王强 | Hits:

[Other] Xilinx-FIRfilter-iP

Description: Xilinx IP核设计FIR滤波器,调用IP核实现FIR滤波器，相关具体步骤还有Verilog HDL的相关代码-verilog HDL
Platform: | Size: 346112 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] fir-ip-vhdl

Description: altera quartus fir ip核 vhdl程序含测试文件-altera quartus fir ip nuclear vhdl program including test files
Platform: | Size: 3072 | Author: bambod | Hits:

[VHDL-FPGA-Verilog] 20140825

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 5541888 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 6000640 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] qam16-TX

Description: 基于Altera MAX10 FPGA的QAM16发送端设计代码，其中采用了MAX10 Fir滤波器IP核。供相关设计人员参考，或者进一步咨询本人。-Based on Altera MAX10 FPGA design of QAM16 the sender code, which uses the MAX10 Fir filter IP core. Related reference for designers, or further consultation himself.
Platform: | Size: 22528 | Author: zhang | Hits:

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