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[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[VHDL-FPGA-Verilog] ise

Description: FPGA/CPLD设计工具---Xilinx ISE使用详解光盘源代码，Xilinx公司推荐的FPGA/CPLD培训教材-FPGA/CPLD design tools-Xilinx ISE explain the use of CD-ROM source code, Xilinx Inc. recommended FPGA/CPLD training materials
Platform: | Size: 22214656 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] ISE

Description: 学习Xilinx公司开发软件ISE的基础资料，从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.
Platform: | Size: 51340288 | Author: wl | Hits:

[VHDL-FPGA-Verilog] ddc_FPGA

Description: 简要介绍了数字下变频的设计，通过采用xilinx的ise软件，ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
Platform: | Size: 2578432 | Author: 望天 | Hits:

[Windows Develop] ISE

Description: XINILX最新开发软件版本,ISE11.1,这里的资源最好,比讯雷快得多 -XINILX latest development software version, ISE11.1, where the resources of the best, much faster than the Thunder
Platform: | Size: 477184 | Author: 汪翔 | Hits:

[VHDL-FPGA-Verilog] xilinx_ise_12

Description: 最新xilinx_ISE-12.3 version License 扩展名.lic-xilinx_ISE-12.3 version License
Platform: | Size: 5120 | Author: TBR | Hits:

[SCM] XILINX-ISE-MODELSIN-SE-Simulation

Description: Modelsim 10.0a 中建立 Xilinx ISE 13.1的仿真库及其之间调用设置详解。-Modelsim 10.0a create Xilinx 13.1 calls between the simulation library and its setting Detailed.
Platform: | Size: 478208 | Author: 迷失De信仰 | Hits:

[VHDL-FPGA-Verilog] ISE-Design-Suite-13

Description: 这是ise10.1的实用说明，上面有好多的有用东西，希望对朋友们有所帮助-This is ise10.1 practical note, the above there are a lot of useful things, want to help friends
Platform: | Size: 301056 | Author: 飞飞 | Hits:

[VHDL-FPGA-Verilog] eetop.cn_licgen_ise_13.1

Description: this the license genarator for xilinx ISE DESIGN SUIT 13.1 -this is the license genarator for xilinx ISE DESIGN SUIT 13.1
Platform: | Size: 292864 | Author: raghul | Hits:

[VHDL-FPGA-Verilog] VCO

Description: 压控振荡器的FPGA实现，Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
Platform: | Size: 1024 | Author: 法克尤 | Hits:

[VHDL-FPGA-Verilog] sp605_MIG_rdf0029_13.1_c

Description: ISE MIG（DDR3）使用方法，ISE版本为13.1-MIG user guide
Platform: | Size: 6471680 | Author: John | Hits:

[Other] ise13.1

Description: introduce how to use xilinx ISE 13.1
Platform: | Size: 2203648 | Author: 孙明 | Hits:

[ARM-PowerPC-ColdFire-MIPS] xilinx-ise-13.1-operation-flow

Description: 此文档介绍了如何在xilinx ise 13.3的开发环境里面进行开发，并将程序下载到xilinx fpga里面-This document describes how to development, and download the program to the inside of xilinx fpga xilinx ise 13.3 development environment inside
Platform: | Size: 1879040 | Author: nx74110 | Hits:

[Other] TEST_RAM2

Description: test ram. vhdl nexys2 ISE 13.1
Platform: | Size: 1024 | Author: nobitatk21 | Hits:

[VHDL-FPGA-Verilog] ml605_PCIe_Gen1_x8_rdf0008_13.2_c

Description: 基于ML605开发板生成的x8 PCIE验证程序，可在ISE 13.2上正常运行，用户可根据自身需求进行修改-ML605 development board based on the generated x8 PCIE verification process can be run properly in ISE 13.2, the user can modify according to their needs
Platform: | Size: 4032512 | Author: aj | Hits:

[VHDL-FPGA-Verilog] my_uart2

Description: 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Summary ---------------- INFO:WebTalk:1- WebTalk is enabled because you are using a WebPACK license. INFO:WebTalk:8- WebTalk Install setting is ON. INFO:WebTalk:6- WebTalk User setting is ON. INFO:WebTalk:5- D:/Xilinxsheji/my_uart2/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at D:/xilinx13.2/ISE_DS/ISE/data/reports/webtalk_introduction.html
Platform: | Size: 253952 | Author: chen | Hits:

[hardware design] license

Description: Xilinx ISE13.1破解器，能够对XilinxISE13.1软件进行破解-Xilinx ISE 13.1 software cracker, generate license files, ISE13.1 crack
Platform: | Size: 292864 | Author: torry lee | Hits:

[Other] ISE_13.2CRACK

Description: ISE 13.2可破解在自己电脑内运行，将自动生成破解文件.lic，复制到安装目录下，在注册机中添加即可’(SE 13.2 can be cracked in their own computer running, will automatically generate crack file.Lic, copy to the installation directory, add in the registration machine can be)
Platform: | Size: 292864 | Author: tcxz111 | Hits:

[VHDL-FPGA-Verilog] xilinx_lib.tar

Description: 用于modelsim仿真的xilinxfpga平台IP库，以ise 13.x为基础制作，在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
Platform: | Size: 16146432 | Author: asmreg | Hits:

[VHDL-FPGA-Verilog] VmodCAM_Ref_HD Demo_13

Description: This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup. The project configures the two cameras on the VmodCAM for maximum resolution and frame rate, RGB output and video snapshot mode. The DDR memory on-board the Atlys is used as a frame buffer. The two video feeds from both cameras are bufferd in the DDR, while the FPGA drives the HDMI out port with either of the cameras. Switch 7 selects the camera which gets displayed. The resolution of the cameras (1600x1200) gets cropped to fit the display resolution of 1600x900. Project built in ISE 13.2, tested in ISE 13.1.
Platform: | Size: 13762560 | Author: domnish | Hits:
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