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[source in ebook] 静态存储器

Description: 在FPGA设计IP核中，很有用
Platform: | Size: 622553 | Author: mengly1985@126.com | Hits:

[Other] ISE使用指南(完整版)

Description: ISE简要介绍 Xilinx是全球领先的可编程逻辑完整解决方案的供应商，研发、制造并销售应用范围广泛的高级集成电路、软件设计工具以及定义系统级功能的IP（Intellectual Property）核，长期以来一直推动着FPGA技术的发展。Xilinx的开发工具也在不断地升级，由早期的Foundation系列逐步发展到目前的ISE 9.1i系列，集成了FPGA开发需要的所有功能，其主要特点有： • 包含了Xilinx新型SmartCompile技术，可以将实现时间缩减2.5倍，能在最短的时间内提供最高的性能，提供了一个功能强大的设计收敛环境； • 全面支持Virtex-5系列器件（业界首款65nm FPGA）； • 集成式的时序收敛环境有助于快速、轻松地识别FPGA设计的瓶颈； • 可以节省一个或多个速度等级的成本，并可在逻辑设计中实现最低的总成本。
Platform: | Size: 5285888 | Author: d.c_superman@163.com | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[VHDL-FPGA-Verilog] convert

Description: 用与生成ISE的IP核的COE文件，一些具体的参数要自己设置一下！
Platform: | Size: 1024 | Author: 1111 | Hits:

[Other] lab2mb

Description: 为硬件设计添加 IP，这个实验将使用 Xilinx 开发平台工作室（XPS）为一个已有的处理器系统添加附加 IP（硬 件功能单元）。你将会学习通过IP目录图标添加附加IP。在实验的最后，你将会创建设计的网络清单，并使用 ISE 来实现设计。-For the hardware design to add IP, this experiment will use the Xilinx Platform Studio (XPS) for an existing system processor to add additional IP (hardware functional unit). You will be learning through the IP catalog icons to add additional IP. Finally in the experiment, you will create the design of network inventory and to use ISE design.
Platform: | Size: 1482752 | Author: jie | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] DUC

Description: 基于XILINX ISE下的数字上变频设计，其中用到了XILINX的乘法IP。已经通过工程实用，好用。-XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.
Platform: | Size: 18432 | Author: 咚咚 | Hits:

[Documents] dds_test

Description: 此程序在于，调用ISE中自带的DDS__IP，来产生单正弦信号，该程序已通过布线后仿真实现-The program focus on that it utilize the DDS core embedded in the ISE to generate the sigle sinusoid signal and this program have acess to the posted simulation!
Platform: | Size: 1796096 | Author: 艾巍 | Hits:

[Software Engineering] ipcore

Description: XILINX公司ISE自带的IP核，功能介绍，如何使用这些IP核来加快你的开发。-IP release note guide
Platform: | Size: 162816 | Author: 老刘 | Hits:

[Software Engineering] FPGA_RS232

Description: 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction.
Platform: | Size: 215040 | Author: jalon | Hits:

[Books] Block_Memory_Generator_v3.3

Description: Xilinx IP core 生成手册-Block_Memory_Generator
Platform: | Size: 1935360 | Author: wang pu | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
Platform: | Size: 896000 | Author: panzhijian | Hits:

[VHDL-FPGA-Verilog] multiplier_ip

Description: 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
Platform: | Size: 2784256 | Author: chenlan | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] mypro_synfifo

Description: 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
Platform: | Size: 1275904 | Author: Hurley | Hits:

[Other] ise-ip-core

Description: IP核包括硬IP与软IP。调用IP核能避免重复劳动，大大减轻设计人员的工作量。-IP cores, including hard IP and soft IP. IP calls to avoid duplication of nuclear energy, thus greatly reducing the workload of the designer.
Platform: | Size: 352256 | Author: zfj | Hits:

[Other] the-IP-IP-core-solution-of-ISE

Description: ISE IP核详细解释与使用方法，包括接口定义及如何使用列子-the IP IP core solution of ISE
Platform: | Size: 14923776 | Author: 施楠 | Hits:

[VHDL-FPGA-Verilog] 基于IP核的ISE设计流程

Description: 讲述了在ISE中如何通过建立ip核，使用ip核可以增加程序设计的效率。(In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.)
Platform: | Size: 2491392 | Author: jihan | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)
Platform: | Size: 1024 | Author: liyan2020 | Hits:
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