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[VHDL-FPGA-Verilog] jkchu

Description: jk触发器，自己尝试编辑的，用状态机实现，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can
Platform: | Size: 81920 | Author: 谢小川 | Hits:

[VHDL-FPGA-Verilog] djkrs

Description: d,jk,rs触发器的vhdl语言实现，简单明了-d, jk, rs flip-flop of the VHDL language, simple and clear
Platform: | Size: 70656 | Author: 周军 | Hits:

[VHDL-FPGA-Verilog] bhgfdti

Description: 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step addition and subtraction counter
Platform: | Size: 423936 | Author: 俞皓尹 | Hits:

[Other] jk-ff

Description: j-k flip flop implementation in XCS2-j-k flip flop implementation in XCS200
Platform: | Size: 15360 | Author: Amirali | Hits:

[VHDL-FPGA-Verilog] jkff

Description: JK flip-flop is implemented using VHDL
Platform: | Size: 39936 | Author: nik | Hits:

[VHDL-FPGA-Verilog] vhdl_jk

Description: 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
Platform: | Size: 201728 | Author: 刘轶龙 | Hits:

[Windows Develop] DtoJK

Description: Using an edge triggered D flip-flop to implement a JK flip-flop
Platform: | Size: 3072 | Author: PigeonLove Purrrrr | Hits:

[ELanguage] 5

Description: Code for JK flip flop and SR flip flop
Platform: | Size: 1024 | Author: D S Manjunath | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
Platform: | Size: 1024 | Author: 龚成 | Hits:

[Other] cnt8

Description: 用JK-flip-flop做的8进制counter-mod-8-counter
Platform: | Size: 385024 | Author: suhang | Hits:

[Other] jk

Description: jk触发器在rs触发器的基础上进行改进，可以将jk=1的输入状态定义为合法状态。-jk flip-flop in the rs flip-flop based on the improvement can be jk = 1 of the input state is defined as the legal state.
Platform: | Size: 28672 | Author: 李本 | Hits:

[VHDL-FPGA-Verilog] trigger

Description: D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
Platform: | Size: 5120 | Author: 孙斌 | Hits:

[FlashMX] count10

Description: 十进制计数器 自己尝试编辑的，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can-Decimal counter his attempt to edit, and can-jk flip-flop, try to edit their own, using state machine to achieve, you can
Platform: | Size: 106496 | Author: liu jian ming | Hits:

[VHDL-FPGA-Verilog] jk

Description: 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
Platform: | Size: 291840 | Author: 宋茜 | Hits:

[VHDL-FPGA-Verilog] JK

Description: JK触发器的功能实现，采用VHDL编程，可以下载到FPGA中进行演示-JK flip-flop implementation of function, using VHDL programming, you can download a presentation to the FPGA,
Platform: | Size: 1051648 | Author: 风清扬 | Hits:

[VHDL-FPGA-Verilog] JK

Description: 使用jk触发器来实现CMI码的编译码，延时小，操作方便-Using jk flip-flop to achieve the CMI code encoding and decoding, the delay is small, easy to operate
Platform: | Size: 30720 | Author: 华子 | Hits:

[VHDL-FPGA-Verilog] jk

Description: 基于quartus2的jk触发器设计，内含源码和仿真图-Jk flip-flop design based on the quartus2, containing source code and simulation diagram
Platform: | Size: 2048 | Author: huikai | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-jk-flip-flop

Description: vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
Platform: | Size: 11264 | Author: nasimus | Hits:

[VHDL-FPGA-Verilog] JK

Description: 带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器-With reset terminal, set end delay the 15ns CP' s response to the falling edge of the JK flip-flop
Platform: | Size: 32768 | Author: hsdhak | Hits:

[VHDL-FPGA-Verilog] JK-flip-flop

Description: 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language
Platform: | Size: 15360 | Author: chen | Hits:
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