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[Other resource] altera_lcd_controller

Description: quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
Platform: | Size: 26888 | Author: 张建 | Hits:

[Other resource] LCD_IP_code

Description: LCD的通用驱动电路IP核设计..... -generic LCD driver circuit IP Core Design ...
Platform: | Size: 58966 | Author: 肖剑锋 | Hits:

[VHDL-FPGA-Verilog] altera_lcd_controller

Description: quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
Platform: | Size: 26624 | Author: 张建 | Hits:

[Software Engineering] LCD_IP_code

Description: LCD的通用驱动电路IP核设计..... -generic LCD driver circuit IP Core Design ...
Platform: | Size: 58368 | Author: 肖剑锋 | Hits:

[VHDL-FPGA-Verilog] VGA_LCD_IP

Description: vga ipcore的verilog代码
Platform: | Size: 495616 | Author: | Hits:

[SCM] LCD_Controller_Altera_MAX_II_CPLD

Description: 基于MAXII CPLD的对1602字符型液晶进行读写操作，其中使用了一个CFI的IP核-MAXII CPLD-based character LCD on the 1602 to read and write operation, which uses a CFI of the IP core
Platform: | Size: 7168 | Author: jaylee | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] lcd_drv

Description: IP core for LCD controller of Xilinx FPGA
Platform: | Size: 2048 | Author: phong duong | Hits:

[VHDL-FPGA-Verilog] vhdl5

Description: 利用IP core完成2X16字符液晶屏的访问。通过写命令来控制将数据写到哪一行；通过写数据，将数据输出在液晶屏上显示。-Using IP core to complete 2X16 character LCD screen access. By writing the command to control where the data write line by writing the data, output data displayed on the LCD screen.
Platform: | Size: 24576 | Author: 王记存 | Hits:

[VHDL-FPGA-Verilog] LCD_PS2

Description: DE2的鼠标IP核的完整套件。使用altera_up_avalon_ps2。有lcd-Mouse IP core DE2 complete package. Use altera_up_avalon_ps2. There lcd
Platform: | Size: 13129728 | Author: 海到无涯 | Hits:

[VHDL-FPGA-Verilog] mylcdip

Description: lcd vhdl ip 核 挂接在 opb 总线上 可以完美实现 lcd 字符液晶的 驱动。-this is a vhdl lcd character ip core based on OPB （onchip periheral bus）
Platform: | Size: 3593216 | Author: qinjian | Hits:

[Embeded-SCM Develop] 95zlg_avalon_lcd128_64

Description: 周立功公司推出的IP核，此IP核为12864驱动IP核。-ZLG has introduced the IP core, IP core, 12864 drivers for this IP core.
Platform: | Size: 19456 | Author: haha | Hits:

[VHDL-FPGA-Verilog] lcd-ip-core

Description: LCD 驱动的IPCORE，可用于alteraFPGA-LCD driver IPCORE, can be used to alteraFPGA
Platform: | Size: 26624 | Author: 徐湛 | Hits:

[VHDL-FPGA-Verilog] vga_lcd

Description: VGA/LCD控制 ip核，支持 CRT LCD,支持多种色彩方案。-VGA/LCD control ip core, support CRT LCD, supports a variety of color schemes.
Platform: | Size: 611328 | Author: XU | Hits:

[VHDL-FPGA-Verilog] LCDIp

Description: 一款TFT-LCD驱动的IP核，可以嵌入到NIos系统中，可以使用的。-A TFT-LCD driver of the IP core
Platform: | Size: 194560 | Author: 刘富伟 | Hits:

[VHDL-FPGA-Verilog] uartlcd

Description: 通过FPGA的VHDL程序实现对1602液晶的控制，此模块可以作为IP核直接调用-By FPGA VHDL program to achieve the 1602 LCD control module can be called directly as an IP core
Platform: | Size: 1014784 | Author: 刘涛 | Hits:

[ARM-PowerPC-ColdFire-MIPS] TFT-LCD

Description: 基于Nios+II的LCD驱动IP核的设计,IP核altera tft lcd controller -Design of the Nios+II driver IP core based on LCD, IP core TFT LCD controller Altera
Platform: | Size: 2948096 | Author: liven | Hits:

[VHDL-FPGA-Verilog] my_second_fpga

Description: 用Quartus ii13.0写的二进制加法器，使用了IP核RAM，以及LCD显示，打开就能直接使用。-Using Quartus ii13.0 write binary adder, using the IP core RAM, and LCD display, open can be used directly.
Platform: | Size: 6053888 | Author: | Hits:

[VHDL-FPGA-Verilog] LCD-IP-CORE

Description: LCD Controller IP for Xilinx FPGA
Platform: | Size: 355328 | Author: Eddie | Hits:

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