Search - lcd vhdl 16

[SCM] chuanxing_char_LCD

Description: 凌阳十六位单片机的LCD串行汇编代码。LCD型号为HD44780-Sunplus 16 LCD MCU serial code compilation. LCD models for HD44780
Platform: | Size: 5120 | Author: 丁运鸿 | Hits:

Description: 程序实现的功能是标准的16×2字符型液晶模块上显示Welcome RedLogic World!字符串-Realize the function of the procedure is a standard 16 × 2 character LCD module to display Welcome RedLogic World! String
Platform: | Size: 333824 | Author: bayernb | Hits:

[VHDL-FPGA-Verilog] LCD1602

Description: LCD1602显示源代码 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是标准的16×2字符型液晶模块上显示字符串； 3-LCD1602 display the source code 1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is a standard 16 × 2 character LCD module to display the string 3
Platform: | Size: 716800 | Author: 张海风 | Hits:

[VHDL-FPGA-Verilog] lcd240128_ok

Description: 基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using
Platform: | Size: 793600 | Author: 陈泽涛 | Hits:

[source in ebook] LCD_VHDL

Description: 液晶模块输出VHDL程序程序实现的功能是标准的16×2字符型液晶模块上显示字符串-LCD module output VHDL procedures to achieve the function of the procedure is a standard 16 × 2 character LCD module to display the string
Platform: | Size: 436224 | Author: zl.yin | Hits:

[VHDL-FPGA-Verilog] VHDL_1602

Description: 显示LCD,采用VHDL语言编写，基于1602的显示模块-Display LCD, using VHDL language, based on the 1602 display module
Platform: | Size: 1594368 | Author: lk | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] bin_copy

Description: FPGA驱动12864汉字显示源代码，12864是16个引脚的带字库的液晶显示模块-12864 Chinese character display FPGA-driven source code, 12864 is a 16-pin LCD display module with a font
Platform: | Size: 3276800 | Author: tdgyh | Hits:

[VHDL-FPGA-Verilog] LCD-core

Description: 基于wb总线的支持16*2的LCD驱动-based on wb bus lcd
Platform: | Size: 7168 | Author: 王东 | Hits:

[VHDL-FPGA-Verilog] lcdasegaled

Description: lcd显示跑马灯显示七段数码管计时 12232F是一种内置8192个16*16点汉字库和128个16*8点ASCII字符集图形点阵液晶显示器,它主要由行驱动器/ 列驱动器及128×32全点阵液晶显示器组成。可完成图形显示,也可以显示7.5×2个(16×16点阵)汉字.与外部CPU接口采用并行或串行方式控制。-lcd display Seven-Segment LED Display Marquee is a built-in timing 12232F 8192 16* 16 points and 128 Chinese character library 16* 8 ASCII character set dot matrix liquid crystal display, which is mainly from the line driver/line driver and 128 × 32 full dot matrix liquid crystal display components. Complete graphical display can also show 7.5 × 2 个 (16 × 16 dot) character. And the external CPU interface with parallel or serial control.
Platform: | Size: 1107968 | Author: wws | Hits:

[VHDL-FPGA-Verilog] lcd

Description: 基于fpga的tft液晶驱动，控制器是ILI9325，是verilog写的，16位并口模式，我上网上搜索了很久都没找到的，-Fpga based on the tft LCD driver, controller ILI9325, is written in verilog, 16-bit parallel mode, on-line search for a long time I did not find,
Platform: | Size: 3734528 | Author: 第三方 | Hits:

[VHDL-FPGA-Verilog] LCD

Description: VHDL-FPGA-Verilog LCD charachteri 2*16 sample program
Platform: | Size: 333824 | Author: farshad | Hits:

[Com Port] UART_VHDLCodes

Description: 基于VHDL的异步串口收发器，在FPGA上设计Uart接收模块实现从pc接收串口数据；在FPGA上设计Uart发送模块，把从pc接收的数据的16进制值加1再发送给PC；设计单片机和FPGA接口模块，把接收到的数据送给单片机，并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data design the Uart send module on FPGA, the hexadecimal value of the data received from the pc plus 1 and then sent to a PC design microcontroller and FPGA interface module, the received data sent to the MCU, and displayed on the LCD
Platform: | Size: 427008 | Author: katheqiu | Hits:

[VHDL-FPGA-Verilog] AVA6SV2_LCD

Description: Vhdl Code for lcd 16*2 . display text and how to rotate a text in lcd with pure vhdl code
Platform: | Size: 80896 | Author: mehdi | Hits:

[Software Engineering] lcd

Description: vhdl code fpga for lcd 2*16
Platform: | Size: 884736 | Author: mrelec | Hits:

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[SCM] chuanxing_char_LCD

[source in ebook] LCD_VHDL

[VHDL-FPGA-Verilog] LCD1602

[VHDL-FPGA-Verilog] lcd240128_ok

[source in ebook] LCD_VHDL

[VHDL-FPGA-Verilog] VHDL_1602

[Video Capture] camera_up

[VHDL-FPGA-Verilog] bin_copy

[VHDL-FPGA-Verilog] LCD-core

[VHDL-FPGA-Verilog] lcdasegaled

[VHDL-FPGA-Verilog] lcd

[VHDL-FPGA-Verilog] LCD

[Com Port] UART_VHDLCodes

[VHDL-FPGA-Verilog] AVA6SV2_LCD

[Software Engineering] lcd

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