Description: 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off. Platform: |
Size: 1041408 |
Author:ryan |
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Description: 本教程主要分为以下几个部分，Max+plusⅡ和QuartusⅡ软件介绍；组合逻辑电路实验；时序逻辑电路实验；数字电路系统设计实验（高级实验）；实践训练项目。数字电路系统设计实验和实践训练项目可以选作为课程设计或课程实训的项目。课程设计或课程实训也可以利用硬件提供的MCU 单元结合软硬件进行设计。
本教程适用于应用电子技术专业、自动检测与仪表专业、电子信息专业、计算机控制专业、计算机应用专业等专业的电子设计类课程的教学实验及课程设计使用。-This tutorial is divided into the following sections, Max+ plus Ⅱ and software introduced Quartus Ⅱ combinational logic circuit experiment sequential logic circuit experiment digital circuit design experiments (Advanced Experimental) practical training program. Digital circuit design experiments and practical training projects can be chosen as the training curriculum or course design project. Training curriculum or course can also use the combination of hardware, software and hardware to provide the MCU unit design. This tutorial applies to the professional application of electronic technology, automatic detection and Instrument Engineering, Electronic Information, computer control of a professional, computer applications in electronic design professionals and other professional courses in teaching and curriculum design using experimental. Platform: |
Size: 1732608 |
Author:孙 |
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Description: The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconfi gurable logic element are implemented one without extra embedded registration and the other with extra embedded registration. The one with extra embedded registration requires an additional latch but reduces the computing time considerably. Both these versions can be configured as any one of the 27 fundamental NCL gates, including the resettable and inverting variations. The two approaches are compared with each other showing that the version with extra embedded registration requires less computing time than the version without extra embedded registration. -The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconfi gurable logic element are implemented one without extra embedded registration and the other with extra embedded registration. The one with extra embedded registration requires an additional latch but reduces the computing time considerably. Both these versions can be configured as any one of the 27 fundamental NCL gates, including the resettable and inverting variations. The two approaches are compared with each other showing that the version with extra embedded registration requires less computing time than the version without extra embedded registration.
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Size: 6144 |
Author:Nagendran |
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Description: 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA.
(1) Synthesize and verify (simulate) the VHDL design of the FIFOs
(2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells) and PTs (product terms) are needed? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.
(3) For FPGA implementation (place and route) of the FIFOs, how many LBs (logic blocks)? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.
(4) Try to synthesize again the design with timing constraints and compare with its former counterparts. You will create the timing constraint file by yourself and add it to your project. Please refer to the following graphic interface of ISE:
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Size: 115712 |
Author:魏攸 |
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Description: 1、掌握运算器的数据传输方式。
2、掌握74LS181的功能和应用。
3、学习并掌握利用CPLD器件通过原理图进行算术逻辑单元的设计。
1、完成16位不带进位位算术、逻辑运算实验。按照实验步骤完成实验项目，了解算术逻辑运算单元的运行过程。
2、通过原理图配置EPM7128的内部电路结构，使其替代分离的算术逻辑运算单元的设计。
-A master computing device data transmission. 2, to grasp the features and applications of the 74LS181. To learn and master the use of the CPLD device through the schematic design of the arithmetic logic unit. 1 to complete the 16 into a bit arithmetic and logic operations experiments. Completion of the pilot project, in accordance with the experimental procedures and understanding of arithmetic and logic unit is running. 2, the schematic configuration the EPM7128 the internal circuit structure it to replace the design of the separation of arithmetic and logic unit. Platform: |
Size: 1361920 |
Author:冷色系绝恋 |
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Description: KeilC 编写的程序，基于80C51芯片+12864液晶屏幕硬件平台，实现贪食蛇程序的例子，包含液晶矩阵键盘驱动，逻辑控制层次的程序代码。由此理解可是顺利移植到其他平台上。附带的protues程序可以调用生成的hex文件观看硬件显示效果。-On the platform of 80C51+12864LCD，the program project can easily implete simple Gluttonous Snake Game funtion.This is a Keil C
project including the drivers of LCD and Keyboard,and he logic control funtion of the Game, which can be easily transplant on other hardware plateform. The final circuit result can be shown on the protues design only if the chip is connect to the hex file generated by the project.
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Size: 126976 |
Author:谢翔 |
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Description: We want to show the values set through the switches SW8-1 on the 7-segment display and HEX0 Hex1. Values are denoted SW4 and SW8-5-one, shown in Hex1 and diplays HEX0, respectively. Your circuit must be able to show the digits 0 to 9, and deal values in 1010 to 1111 as "does not matter".
1. Create a new project that will be used to implement the desired circuit on board EXSTO. The intent of this exercise is to manually derive the logic functions necessary for the 7-segment displays. You should use simple expressions in your VHDL code and specify each logic function as a boolean expression.
2. Write a VHDL code that provides the required functionality. Include this code in your project and assign the pins on the FPGA to connect properly to the keys and displays, as shown in the Manual of FPGA board.
3. Compile the project and save the compiled circuit in FPGA chip.
4. Test the functionality of your design triggering the keys and watching the displays.-We want to show the values set through the switches SW8-1 on the 7-segment display and HEX0 Hex1. Values are denoted SW4 and SW8-5-one, shown in Hex1 and diplays HEX0, respectively. Your circuit must be able to show the digits 0 to 9, and deal values in 1010 to 1111 as "does not matter".
1. Create a new project that will be used to implement the desired circuit on board EXSTO. The intent of this exercise is to manually derive the logic functions necessary for the 7-segment displays. You should use simple expressions in your VHDL code and specify each logic function as a boolean expression.
2. Write a VHDL code that provides the required functionality. Include this code in your project and assign the pins on the FPGA to connect properly to the keys and displays, as shown in the Manual of FPGA board.
3. Compile the project and save the compiled circuit in FPGA chip.
4. Test the functionality of your design triggering the keys and watching the displays. Platform: |
Size: 1024 |
Author:Lais |
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