Description: This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
File list (Check if you may need any files):
电路图设计
..........\Clock
..........\.....\Clock.asm.rpt
..........\.....\Clock.bdf
..........\.....\Clock.cdf
..........\.....\Clock.done
..........\.....\Clock.dpf
..........\.....\Clock.fit.rpt
..........\.....\Clock.fit.smsg
..........\.....\Clock.fit.summary
..........\.....\Clock.flow.rpt
..........\.....\Clock.map.rpt
..........\.....\Clock.map.summary
..........\.....\Clock.pin
..........\.....\Clock.pof
..........\.....\Clock.qpf
..........\.....\Clock.qsf
..........\.....\Clock.qws
..........\.....\Clock.sof
..........\.....\Clock.tan.rpt
..........\.....\Clock.tan.summary
..........\.....\db
..........\.....\..\Clock.asm.qmsg
..........\.....\..\Clock.asm_labs.ddb
..........\.....\..\Clock.cbx.xml
..........\.....\..\Clock.cmp.cdb
..........\.....\..\Clock.cmp.hdb
..........\.....\..\Clock.cmp.kpt
..........\.....\..\Clock.cmp.logdb
..........\.....\..\Clock.cmp.rdb
..........\.....\..\Clock.cmp.tdb
..........\.....\..\Clock.cmp0.ddb
..........\.....\..\Clock.dbp
..........\.....\..\Clock.db_info
..........\.....\..\Clock.eco.cdb
..........\.....\..\Clock.fit.qmsg
..........\.....\..\Clock.hier_info
..........\.....\..\Clock.hif
..........\.....\..\Clock.map.cdb
..........\.....\..\Clock.map.hdb
..........\.....\..\Clock.map.logdb
..........\.....\..\Clock.map.qmsg
..........\.....\..\Clock.pre_map.cdb
..........\.....\..\Clock.pre_map.hdb
..........\.....\..\Clock.psp
..........\.....\..\Clock.rtlv.hdb
..........\.....\..\Clock.rtlv_sg.cdb
..........\.....\..\Clock.rtlv_sg_swap.cdb
..........\.....\..\Clock.sgdiff.cdb
..........\.....\..\Clock.sgdiff.hdb
..........\.....\..\Clock.signalprobe.cdb
..........\.....\..\Clock.sld_design_entry.sci
..........\.....\..\Clock.sld_design_entry_dsc.sci
..........\.....\..\Clock.syn_hier_info
..........\.....\..\Clock.tan.qmsg
..........\clock1
..........\......\clock1.asm.rpt
..........\......\Clock1.bdf
..........\......\clock1.cdf
..........\......\clock1.done
..........\......\clock1.dpf
..........\......\clock1.fit.rpt
..........\......\clock1.fit.smsg
..........\......\clock1.fit.summary
..........\......\clock1.flow.rpt
..........\......\clock1.map.rpt
..........\......\clock1.map.summary
..........\......\clock1.pin
..........\......\clock1.pof
..........\......\clock1.qpf
..........\......\clock1.qsf
..........\......\clock1.qws
..........\......\clock1.sof
..........\......\clock1.tan.rpt
..........\......\clock1.tan.summary
..........\......\db
..........\......\..\clock1.asm.qmsg
..........\......\..\clock1.asm_labs.ddb
..........\......\..\clock1.cbx.xml
..........\......\..\clock1.cmp.cdb
..........\......\..\clock1.cmp.hdb
..........\......\..\clock1.cmp.kpt
..........\......\..\clock1.cmp.logdb
..........\......\..\clock1.cmp.rdb
..........\......\..\clock1.cmp.tdb
..........\......\..\clock1.cmp0.ddb
..........\......\..\clock1.dbp
..........\......\..\clock1.db_info
..........\......\..\clock1.eco.cdb
..........\......\..\clock1.fit.qmsg
..........\......\..\clock1.hier_info
..........\......\..\clock1.hif
..........\......\..\clock1.map.cdb
..........\......\..\clock1.map.hdb
..........\......\..\clock1.map.logdb
..........\......\..\clock1.map.qmsg
..........\......\..\clock1.pre_map.cdb
..........\......\..\clock1.pre_map.hdb
..........\......\..\clock1.psp
..........\......\..\clock1.rtlv.hdb
Download