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[VHDL-FPGA-VerilogLVDS_Serdes_list_FPGA1

Description: FPGA之间的LVDS传输,采用serdes接口,传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
Platform: | Size: 14338048 | Author: linpingping | Hits:

[VHDL-FPGA-VerilogLVDS_DDR_List_FPGA2

Description: FPGA芯片与ADI公司的AD9779之间的通信,总共有四个通道,68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
Platform: | Size: 808960 | Author: linpingping | Hits:

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